Table of Contents
Advertisement
USB Device Controller
Figure 18.
Endpoint 0 RX Interrupt Handler
Endpoint 0 RX handler
Write EP_NUM register:
− EP_NUM.EP_NUM = 0
− EP_NUM.EP_DIR = 0
− EP_NUM.EP_SEL = 1
− EP_NUM.SETUP_SEL = 0
STAT_FLG.
ACK bit set?
No. Must be STAT_FLG.STALL.
Is LH-initiated stall
and can remove halt
condition?
152
Universal Serial Bus (USB)
Control
Yes
Yes
read flag set
?
No
Read non-ISO RX
FIFO data.
Decrement
wlength_count value by
nb of received bytes.
Write EP_NUM register:
− EP_NUM.EP_NUM = 0
− EP_NUM.EP_DIR = 0
− EP_NUM.EP_SEL = 0
− EP_NUM.SETUP_SEL = 0
No
No
Want to stall
the command
?
Yes
Set
SYSCON2.STALL_CMD
bit to stall the
command.
Yes
Set CTRL.CIR_HALT
bit to 1.
Application-
specific actions
to complete
control read
If control write data stage (OUT
transactions on EP0) is out of control,
write data stage and control read
status stage are automatically
stalled by the core.
wlength_count is 0 (OUT
transactions with more bytes
than expected are
automatically stalled by the
core).
No
wlength_count
> 0?
Yes
Ready to
Yes
receive more
data?
Want to go
out of the ISR
?
Yes
Enable NAK interrupt
by setting
SYSCON1.NAK_EN bit
to 1 if not enabled.
Application
specific action
to resolve stall
No
Write EP_NUM register:
− EP_NUM.EP_NUM = 0
− EP_NUM.EP_DIR = 0
− EP_NUM.EP_SEL = 0
− EP_NUM.SETUP_SEL = 0
Prepare for
control write
status stage
Set
CTRL.SET_FIFO_EN bit
to 1.
Wait until ready to
receive data.
Write EP_NUM register:
− EP_NUM.EP_NUM = 0
− EP_NUM.EP_DIR = 0
− EP_NUM.EP_SEL = 0
− EP_NUM.SETUP_SEL = 0
End of endpoint 0 RX
handler
SPRU761A
Advertisement
Chapters
Table of Contents
