Operations; Digital Filter - Renesas M16C/64A Series User Manual

M16C/64A Group
7.4

Operations

7.4.1

Digital Filter

A digital filter can be used to monitor VCC1 input voltage. For the voltage detector i (i = 1 to 2), the
digital filter is enabled when the VWiC1 bit in the VWiC register is set to 0 (digital filter enabled).
fOCO-S divided by 1, 2, 4, or 8 is selected as a sampling clock. When using the digital filter, set the
CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on).
The VCC1 input level is sampled by the digital filter for every sampling clock. When the same sampled
level is detected twice in a row, at the next sampling timing, the internal reset signal goes low or a
voltage monitor i interrupt request is generated. Therefore, when the digital filter is used, the time from
when the VCC1 input voltage level passes Vdeti until when a reset or an interrupt is generated is up to
three cycles of the sampling clock.
Since fOCO-S stops in stop mode, the digital filter does not function. When using voltage detector i to
exit stop mode, set the VWiC1 bit in the VWiC register to 1 (digital filter disabled).
Figure 7.2 shows Digital Filter Operation Example.
VCC1
Vdet1
VW1C3 bit in
the VW1C register
Digital filter
sampling timer
VW1C2 bit in
the VW1C register
Internal signal
(Voltage monitor 1
interrupt request)
The above diagram assumes the following:
• The VW12E bit in the VWCE register is 1 (voltage monitors 1 and 2 enabled).
• The VW1C0 bit in the VW1C register is 1 (voltage monitor 1 interrupt/reset enabled).
• The VW1C1 bit in the VW1C register is 0 (digital filter enabled).
• The VW1C6 bit in the VW1C register is 0 (voltage monitor 1 interrupt at Vdet1 passage).
Figure 7.2 Digital Filter Operation Example
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Up to 3 cycles of the sampling clock Up to 3 cycles of the sampling clock
Set to 0
7. Voltage Detector
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