Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1447

The USB controller then sends a SETUP token followed by the 8-byte command to endpoint 0 of the ad-
dressed device, retrying as necessary.
3. At the end of the attempt to send the data, the USB controller generates an endpoint 0 interrupt (for example,
set USB_INTRTXE.EP0). The processor core then reads the
whether the USB_EP0_CSR[n]_H.RXSTALL, USB_EP0_CSR[n]_H.TOERR, or the
USB_EP0_CSR[n]_H.NAKTO bits are set.
If USB_EP0_CSR[n]_H.RXSTALL=1, the target did not accept the command (for example, because the
target device does not support it) and issues a stall response.
If USB_EP0_CSR[n]_H.TOERR=1, the USB controller tried to send the SETUP packet and the following
data packet three times without getting a response.
If USB_EP0_CSR[n]_H.NAKTO=1, the USB controller received a NAK response to each attempt to send
the SETUP packet, for longer than the time set in the
controller to either clear the USB_EP0_CSR[n]_H.NAKTO bit to continue trying this transaction (until it
times out again) or to flush the FIFO to abort the transaction before clearing the
USB_EP0_CSR[n]_H.NAKTO bit.
4. If none of USB_EP0_CSR[n]_H.RXSTALL, USB_EP0_CSR[n]_H.TOERR or
USB_EP0_CSR[n]_H.NAKTO bits are set, the SETUP phase is correctly acknowledged. The processor core
can proceed to the following IN data phase, OUT data phase or IN status phase specified for the particular
standard device request.
IN Data Phase as a Host
The processor core driving the host device performs the following actions for the IN data phase of a control transac-
tion.
1. Set the USB_EP0_CSR[n]_H.REQPKT bit.
2. Wait while the USB controller sends the IN token and then receives the required data back.
3. When the USB controller generates the endpoint 0 interrupt (for example, by setting the
USB_INTRTXE.EP0 bit), read the
USB_EP0_CSR[n]_H.RXSTALL bit, the USB_EP0_CSR[n]_H.TOERR bit, the
USB_EP0_CSR[n]_H.NAKTO bit, or the USB_EP0_CSR[n]_H.RXPKTRDY bit is set.
If USB_EP0_CSR[n]_H.RXSTALL=1, the target has issued a stall response.
If USB_EP0_CSR[n]_H.TOERR=1, the USB controller has tried to send the required IN token three times
without getting a response.
If USB_EP0_CSR[n]_H.NAKTO=1, the USB controller has received a NAK response to each attempt to
send the IN token, for longer than the time set in the
controller to either clear the USB_EP0_CSR[n]_H.NAKTO bit to continue trying this transaction (until it
times out again) or clear USB_EP0_CSR[n]_H.REQPKT before clearing the
USB_EP0_CSR[n]_H.NAKTO bit to abort the transaction.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
USB_EP0_NAKLIMIT[n]
USB_EP0_CSR[n]_H
USB_EP0_NAKLIMIT[n]
USB_EP0_CSR[n]_H
register. Direct the USB
register. Determine whether the
register. Direct the USB
Host Mode
register to establish
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