Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1448

Host Mode
4. If the USB_EP0_CSR[n]_H.RXPKTRDY bit is set, the processor core reads the data from the endpoint 0
FIFO, then clears USB_EP0_CSR[n]_H.RXPKTRDY.
5. If further data is expected, the processor core must repeat the previous steps.
When all the data is successfully received, the processor core can proceed to the OUT status phase of the con-
trol transaction.
OUT Data as a Host (Control)
The processor core driving the host device performs the following actions for the OUT data phase of a control trans-
action.
1. Load the data to be sent into the endpoint 0 FIFO.
2. Set the USB_EP0_CSR[n]_H.TXPKTRDY bit.
The USB controller sends an OUT token followed by the data from the FIFO to endpoint 0 of the addressed
device, retrying as necessary.
3. At the end of the attempt to send the data, the USB controller generates an endpoint 0 interrupt (for example
by setting the USB_INTRTX.EP0 bit). The processor core can then read the
tablish whether the USB_EP0_CSR[n]_H.RXSTALL bit, the USB_EP0_CSR[n]_H.TOERR bit, or the
USB_EP0_CSR[n]_H.NAKTO bit is set.
If USB_EP0_CSR[n]_H.RXSTALL=1, the target has issued a stall response.
If USB_EP0_CSR[n]_H.TOERR=1 the USB controller has tried to send the OUT token and the following
data packet three times without getting a response.
If USB_EP0_CSR[n]_H.NAKTO=1, the USB controller has received a NAK response to each attempt to
send the OUT token, for longer than the time set in the
controller to either clear the USB_EP0_CSR[n]_H.NAKTO bit to continue trying this transaction (until it
times out again) or to flush the FIFO to abort the transaction before clearing the
USB_EP0_CSR[n]_H.NAKTO bit.
If none of the USB_EP0_CSR[n]_H.RXSTALL, USB_EP0_CSR[n]_H.TOERR, or
USB_EP0_CSR[n]_H.NAKTO bits are set, the OUT data is correctly acknowledged.
4. If further data must be sent, the processor core must repeat the previous steps.
When all the data is successfully sent, the processor core proceeds to the IN status phase of the control transac-
tion.
IN Status Phase as a Host (Following SETUP Phase or OUT Data Phase)
The processor core driving the host device performs the following actions for the IN status phase of a control trans-
action.
1. Set the USB_EP0_CSR[n]_H.STATUSPKT and USB_EP0_CSR[n]_H.REQPKT bits. These bits must
be set together.
27–36
USB_EP0_NAKLIMIT[n]
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
USB_EP0_CSR[n]_H
register. Direct the USB
to es-