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Register
Bits
Name
Contains the previous value of [COUNT (prior to the start of the last
EAU operation) + the number of EAU cycles for the last EAU
31:0
COUNT
operation]. This register is cleared automatically when a new
command is started.
25.4.4
EAU Interrupt Register
Register Name:
Block
0x7000
Base Address:
The EAU Interrupt Register is a single bit used to read and clear
Register Description:
the EAU interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
31:1
(Reserved)
6
15:1
(Reserved)
EAU InterruptBit
0
INT
0: EAU Interrupt is currently inactive
1: EAU Interrupt is currently active. Write 1 to clear
25.4.5
EAU RAM Registers
The 2-Kbyte EAU RAM can be read and written with certain restrictions. While the EAU
is active, all requests for reads and writes to the RAM will be ignored. The RAM will not
be reset after a power-on or pin reset assertion. The content of the RAM is
indeterminate until they are initialized by the CPU / Intel XScale processor.
Writes to the RAM are all 32-bit, and are triggered by a half-word write to a RAM
address that is the high half of the word. The required usage model is to write a 4-byte
word two bytes at a time from least significant half-word to most significant half-word.
In actual implementation, the register interface stores the bottom two bytes in a write
buffer until the two high bytes are written. Repeated high half-word writes (at other
addresses) will initialize other 32-bit words with half of the writes required to initialize
all bytes individually. Do not attempt to write a byte to the RAM: byte writes trigger a
pre-read operation, as described below, and the data in the write buffer is ignored.
Reads to the RAM are also buffered and accessed with different timing than reads to
registers. Reading values from the EAU takes several cycles, and during this time the
Intel XScale processor is held off. using EAU_DONE. The EAU RAM resides at memory
locations as shown in
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
918
®
®
Intel
IXP45X and Intel
Description
Offset Address
(Reserved)
Description
Table 290, "EAU RAM Memory Locations" on page
IXP46X Product Line of Network Processors—Exponentiation
EAU Count Register
EAUINT
_200C
EAU Status Register
Acceleration Unit
Reset
Access
Value
0x00
RO
0x0000_0000
Reset Value
Access:
(See below.)
8
7
6
5
4
3
2
1
Reset
Access
Value
0x00
0x00
0x0
RW
919.
August 2006
Order Number: 306262-004US
0
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