Supported Ddri Sdram Extended Mode Register Settings - Intel IXP45X Developer's Manual

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Memory Controller—Intel
The MCU then places all of the following data outputs and strobes in the High-Z
state:
DDRI_DQS[4:0], DDRI_DQ[31:0], DDR_CB[7:0]
The MCU deasserts DDRI_CKE[1:0] for a minimum of 200 us after supply voltage
reaches the desired level. Asserting PWRON_RESET_N achieves this state.
4. The MCU then performs sixteen RCOMP calibration cycles which take an additional
34 ms. Software MUST wait until this time has elapsed before continuing with DDRI
SDRAM initialization.
5. Software overwrites the default value of register DDR_RCOMP_CSR3 (Hex Offset
Address = 0x0CC00 F570) with a new value of 0x0000 1000.
6. Software overwrites the default value of register DDR_DRIVE3 (Hex Offset Address
= 0x0CC00 F5AC) with a new value of 0x0002 08F0.
7. Software disables the refresh counter by setting the RFR to zero.
8. Software issues one NOP cycle after the 200 us device deselect. A NOP is
accomplished by setting the SDIR to 0011
the NOP.
9. Software issues a precharge-all command to the DDRI SDRAM interface by setting
the SDIR to 0010
10. Software issues an extended-mode-register-set command to enable the DLL by
writing 0100
parameters:
a. DLL = Enable/Disable
b. Additive Latency (AL) is always zero for the IXP45X/IXP46X network
Figure 106. Supported DDRI SDRAM Extended Mode Register Settings
The DDR SDRAM Extended Mode Register resides
in the DDR SDRAM devices.
Note:
DDRI_BA[1:0] must be 01
A12 doesn't exist for 128 Mbit Technology
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
.
2
to the SDIR. The MCU supports the following DDRI SDRAM mode
2
processors. The MCU only supports an AL of zero because the MCU
does not support back-to-back Active to Read or Write commands that
would otherwise be in violation of tRCD (Active to Read/Write
command delay): tRCD is obeyed at all times. Thus, Write Latency
(WL) is always defined as shown in
A12
0 0
to select the Extended Mode Register.
2
. The MCU asserts DDRI_CKE[1:0] with
2
Figure 112 on page
A6
0 0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
605.
A3 A0
DLL Enable:
0: Enable
1: Disable
B4212-001
Developer's Manual
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