Uart Interrupts - Intel IXP45X Developer's Manual

Universal Asynchronous Receiver-Transmitter (UART)—Intel
Product Line of Network Processors
The Modem-Status Register is used to monitor the status of an external modem or data
set. The Modem Status Register is an 8-bit register that is used to detect when a
modem is capable of accepting new data. The status of the modem to accept incoming
data is monitored by reading the Clear-to-Send Bit of the Modem Status Register and
the Delta Clear-to-Send Bit of the Modem Status Register. The other six bits of the
Modem-Status Register can be used for UART debug purposed only.
Modem Status Register Bit 4 is the Clear-to-Send (CTS). The Clear-to-Send Bit will be
the complement of the Clear-to-Send (CTS_N) input signal. The Clear-to-Send signal
will be connected to the Ready-to-Send bit of the Modem Control Register when the
LOOP bit — in the Modem Control Register — is set to logic 1.
• CTS = logic 0 = CTS_N pin is 1
• CTS = logic 1 = CTS_N pin is 0
Modem Status Register Bit 0 is the Delta Clear-to-Send (DCTS). The Delta Clear-to-
Send bit will inform the IXP45X/IXP46X network processors that nothing has happened
to the Clear-to-Send Status since the last time that the Modem-Status Register was
read. The Delta Clear-to-Send bit will be set to logic 0 after a read of the Modem-Status
Register.
• DCTS = logic 0 = No change in CTS_N pin since last read of the Modem-Status
Register
• DCTS = logic 1 = CTS_N pin has changed state since the last read of the Modem-
Status Register
The Modem-Control Register is initialized to hexadecimal 0x00 after reset. The Modem-
Status Register is initialized to hexadecimal 0x00 after reset.
14.4.4

UART Interrupts

The UART Interrupt Enable Register (IER) is an 8-bit register that enables five types of
UART based interrupts and enables the UART functionality and other control
functionality not used by the IXP45X/IXP46X network processors.
UART Interrupt Enable Register bit 6 is the UART Unit Enable (UUE) bit. When the UART
Unit Enable bit is set to logic 0, the UART will be completely non-functional. Likewise,
when the UART Unit Enable bit is set to logic 1, the UART will be enabled.
UART Interrupt Enable Register bits 4 through 0 represent five different interrupt types
that can be individually enabled/disabled:
• Receiver Time Out Interrupt Enable (RTOIE)
• Modem Interrupt Enable (MIE)
• Receiver Line Status Interrupt Enable (RLSE)
• Transmit Data Request Interrupt Enable (TIE)
• Receiver Data Available Interrupt Enable (RAVIE)
The Receiver Line Status Interrupt Enable allows interrupts to be generated to the
Interrupt Controller for the IXP45X/IXP46X network processors and captured in the
UART Interrupt Identification Register (IIR) when a receive error is detected. Such
Receiver Line Status Conditions that would cause the interrupt to occur are:
• Overrun
• Break
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
• Parity
• FIFO error
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
®
IXP46X
• Framing
Developer's Manual
757