Intel IXP45X Developer's Manual page 13

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Contents-Intel IXP45X and Intel
9.10.3 HWHOST............................................................................................. 368
9.10.4 HWDEVICE .......................................................................................... 368
9.10.5 HWTXBUF ........................................................................................... 369
9.10.6 HWRXBUF ........................................................................................... 369
9.11 Host Capability Registers.................................................................................. 370
9.11.1 CAPLENGTH - EHCI Compliant ............................................................... 370
9.11.2 HCIVERSION - EHCI Compliant .............................................................. 370
9.11.3 HCSPARAMS - EHCI Compliant with Extensions ........................................ 370
9.11.4 HCCPARAMS - EHCI Compliant .............................................................. 371
9.11.5 Reserved Register #1 ........................................................................... 372
9.11.6 DCCPARAMS (Non-EHCI) ....................................................................... 372
9.12 Host Operational Registers ............................................................................... 373
9.12.1 USBCMD ............................................................................................. 373
9.12.2 USBSTS .............................................................................................. 375
9.12.3 USBINTR............................................................................................. 377
9.12.4 FRINDEX ............................................................................................. 378
9.12.5 CTRLDSSEGMENT................................................................................. 379
9.12.6 PERIODICLISTBASE .............................................................................. 379
9.12.6.1 Host Controller (PERIODICLISTBASE) ........................................ 379
9.12.7 ASYNCLISTADDR; ENDPOINTLISTADDR .................................................. 380
9.12.7.1 Host Controller (ASYNCLISTADDR) ............................................ 380
9.12.8 BURSTSIZE ......................................................................................... 380
9.12.9 TXFILLTUNING ..................................................................................... 381
9.12.10CONFIGFLAG ....................................................................................... 381
9.12.11PORTSCx ............................................................................................ 382
9.12.11.1Host Controller ....................................................................... 382
9.12.12USBMODE ........................................................................................... 387
9.13 Host Data Structures ....................................................................................... 387
9.13.1 Periodic Frame List ............................................................................... 388
9.13.2 Asynchronous List Queue Head Pointer.................................................... 390
9.13.3 Isochronous (High-Speed) Transfer Descriptor (iTD) ................................. 391
9.13.3.1 Next Link Pointer .................................................................... 392
9.13.3.2 iTD Transaction Status and Control List...................................... 393
9.13.3.3 iTD Buffer Page Pointer List (Plus) ............................................. 394
9.13.4 Split Transaction Isochronous Transfer Descriptor (siTD) ........................... 395
9.13.4.1 Next Link Pointer .................................................................... 395
9.13.4.2 siTD Endpoint Capabilities/Characteristics .................................. 396
9.13.4.3 siTD Transfer State ................................................................. 397
9.13.4.4 siTD Buffer Pointer List (Plus) ................................................... 398
9.13.4.5 siTD Back Link Pointer ............................................................. 398
9.13.5 Queue Element Transfer Descriptor (qTD)................................................ 399
9.13.5.1 Next qTD Pointer .................................................................... 400
9.13.5.2 Alternate Next qTD Pointer....................................................... 400
9.13.5.3 qTD Token ............................................................................. 400
9.13.5.4 qTD Buffer Page Pointer List ..................................................... 403
9.13.6 Queue Head ........................................................................................ 404
9.13.6.1 Queue Head Horizontal Link Pointer........................................... 404
9.13.6.2 Endpoint Capabilities/Characteristics ......................................... 405
9.13.6.3 Transfer Overlay ..................................................................... 407
9.13.7 Periodic Frame Span Traversal Node (FSTN) ............................................ 408
9.13.7.1 FSTN Normal Path Pointer ........................................................ 408
9.13.7.2 FSTN Back Path Link Pointer..................................................... 409
9.14 Host Operational Model .................................................................................... 409
9.14.1 Host Controller Initialization................................................................... 410
9.14.2 Port Routing and Control ....................................................................... 411
9.14.2.1 Port Routing Control via EHCI Configured (CF) Bit ....................... 412
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Intel
®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
13