Actions For Park Mode, Based On Endpoint Response And Residual Transfer State - Intel IXP45X Developer's Manual

Intel
The host controller must apply park mode to queue heads whose EPS field indicates a
high-speed endpoint. The maximum number of consecutive bus transactions a host
controller may execute on a high-speed queue head is determined by the value in the
Asynchronous Schedule Park Mode Count field in the USBCMD register. Software must
not set Asynchronous Schedule Park Mode Enable bit to a one and also set
Asynchronous Schedule Park Mode Count field to a zero. The resulting behavior is not
defined. An example behavioral example describes the operational requirements for the
host controller implementing park-mode. This feature does not affect how the host
controller handles the bus transaction as defined in
Transaction" on page
the current queue head can be executed. All boundary conditions, error detection and
reporting applies as usual. This feature is similar in concept to the use of the Mult field
for high-bandwidth Interrupt for queue heads in the Periodic Schedule.
The host controller effectively loads an internal down-counter PM-Count from
Asynchronous Schedule Park Mode Count when Asynchronous Schedule Park Mode
Enable bit is a one, and a high-speed queue head is first fetched and meets all the
criteria for executing a bus transaction. After the bus transaction, PM-Count is
decremented. The host controller may continue to execute bus transactions from the
current queue head until PM-Count goes to zero, an error is detected, the buffer for the
current transfer is exhausted or the endpoint responds with a flow-control or STALL
handshake.
controller continues with another bus transaction for the current queue head.
Table 176. Actions for Park Mode, Based on Endpoint Response and Residual Transfer
State (Sheet 1 of 2)
PID
IN
OUT
Notes:
1. The host controller may continue to execute bus transactions from the current high-speed queue
head (if PM-Count is not equal to zero), if a PID mismatch is detected (e.g. expected DATA1 and
received DATA0, or visa-versa).
2. This specification does not require that the host controller execute another bus transaction when PM-
Count is non-zero. Implementations are encouraged to make appropriate complexity and
performance trade-offs.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
448
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
444. It only effects how many consecutive bus transactions for
Table 176 summarizes the responses that effect whether the host
Transfer State after
Endpoint
Response
PM-Count
DATA[0,1] w/
Maximum Packet Not zero
sized data
Not zero
Zero
DATA[0,1] w/
Don't care
short packet
NAK Don't care
STALL, XactErr Don't care
ACK Not zero
Not zero
Zero
NYET, NAK Don't care
STALL, XactErr Don't care
Section 9.14.10.3, "Execute
Transaction
Bytes to
Transfer
Allowed to perform another bus
Not Zero
transaction.
Zero Retire qTD and move to next QH
Don't care Move to next QH.
Don't care Retire qTD and move to next QH.
Don't care Move to next QH.
Don't care Move to next QH.
Allowed to perform another bus
Not Zero
transaction.
Zero Retire qTD and move to next QH
Don't' care Move to next QH.
Don't care Move to next QH.
Don't care Move to next QH
Action
1, 2
2
August 2006
Order Number: 306262-004US