Intel IXP45X Developer's Manual page 27

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Contents-Intel IXP45X and Intel
77 PCI Controller Block Diagram................................................................................... 497
78 Type 0 Configuration Address Phase ......................................................................... 502
79 Type 1 Configuration Address Phase ......................................................................... 502
80 Initiated PCI Type-0 Configuration Read Cycle ........................................................... 513
81 Initiated PCI Type-0 Configuration Write Cycle ........................................................... 514
82 Initiated PCI Type-1 Configuration Read Cycle ........................................................... 515
83 Initiated PCI Type-1 Configuration Write Cycle ........................................................... 516
84 Initiated PCI Memory Read Cycle.............................................................................. 516
85 Initiated PCI Memory Write Cycle ............................................................................. 517
86 Initiated PCI I/O Read Cycle .................................................................................... 518
87 Initiated PCI I/O Write Cycle.................................................................................... 519
88 Initiated PCI Burst Memory Read Cycle ..................................................................... 520
89 Initiated PCI Burst Memory Write Cycle..................................................................... 521
90 PCI Controller Arbiter Configuration .......................................................................... 527
91 PCI-to-AHB Address Translation ............................................................................... 531
92 AHB-to-PCI Address Translation - Memory Cycles ...................................................... 533
93 AHB-to-PCI DMA-Transfer Byte Lane Swapping .......................................................... 538
94 PCI-to-AHB DMA-Transfer Byte Lane Swapping .......................................................... 538
95 Byte Lane Routing During PCI Target Accesses of the AHB Bus - Big-Endian AHB Bus ..... 542
96 Byte Lane Routing During PCI Target Accesses of the AHB Bus - Little-Endian AHB Bus ... 543
97 Byte Lane Routing During AHB Slave Accesses of the PCI Bus -
Big-Endian AHB Bus ............................................................................................... 544
98 Byte Lane Routing During AHB Slave Accesses of the PCI Bus -
Little-Endian AHB Bus ............................................................................................. 545
99 Byte Lane Routing During DMA Transfers .................................................................. 546
100 Byte Lane Routing During CSR Accesses.................................................................... 547
101 Memory Controller Block Diagram ............................................................................ 584
102 Dual-Bank DDRI SDRAM Memory Subsystem ............................................................. 589
103 64-Bit to 32-Bit Addressing ..................................................................................... 594
104 Page Hit/Miss Logic for 128/256/512/1, 024-Bit Mode ................................................. 596
105 Logical Memory Image of a DDRI SDRAM Memory Subsystem ...................................... 597
106 Supported DDRI SDRAM Extended Mode Register Settings........................................... 599
107 Supported DDRII SDRAM Extended Mode Register Settings.......................................... 600
108 Supported DDRI SDRAM Mode Register Settings......................................................... 600
109 DDRI SDRAM Initialization Sequence (Controlled with Software)................................... 601
110 MCU Active, Precharge, Refresh Command Timing Diagram ......................................... 603
111 MCU DDR Read Command to Next Command Timing Diagram...................................... 604
112 MCU DDR Write Command to Next Command Timing Diagrams .................................... 605
113 DDRI SDRAM Pipelined Reads .................................................................................. 606
114 DDRI SDRAM Read, 36 Bytes, ECC Enabled, BL=4 ...................................................... 607
115 DDRI SDRAM Write, 36 Bytes, ECC Enabled, BL=4 ..................................................... 610
116 DDRI SDRAM Pipelined Writes.................................................................................. 612
117 Refresh While the Memory Bus is Not Busy ................................................................ 613
118 ECC Write Flow ...................................................................................................... 615
119 IXP45X/IXP46X product line G-Matrix (Generates the ECC) .......................................... 617
120 Sub 64-bit DDRI SDRAM Write (D
121 ECC Read Data Flow ............................................................................................... 621
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122 Intel IXP45X and Intel
(Indicates the Single-Bit Error Location).................................................................... 623
123 Expansion Bus Controller ........................................................................................ 650
124 Chip Select Address Allocation when there are no 32-MByte Devices Programmed .......... 654
125 Expansion Bus Memory Sizing.................................................................................. 654
126 Chip Select Address Allocation when a 32-Mbyte Device is Programmed ........................ 655
127 I/O Wait Normal Phase Timing ................................................................................. 662
128 I/O Wait Extended Phase Timing .............................................................................. 663
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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IXP46X Product Line of Network Processors H-Matrix
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Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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