Pci Controller Interrupts; Byte Lane Routing During Csr Accesses; Pci Interrupt Generation - Intel IXP45X Developer's Manual

®
PCI Controller—Intel IXP45X and Intel
Figure 100. Byte Lane Routing During CSR Accesses
31 24
PCI Data
3
31 24 23
CSR
Register
31 24
CSR
Register
31 24 23
AHB Data
10.3.5

PCI Controller Interrupts

The PCI Controller supports generation of PCI interrupts and interrupts to internal AHB
agents. Complete control of the interrupt sources and enabling is provided using two
registers: the PCI Interrupt Status Register (PCI_ISR) and PCI Interrupt Enable
Register (PCI_INTEN).
10.3.5.1

PCI Interrupt Generation

The PCI Door Bell Register (PCI_PCIDOORBELL) is used to generate a PCI interrupt on
the PCI Bus using the PCI_INTA_N signal. This register is read/write-1-to-set from the
AHB bus, and read/write-1-to-clear from the PCI bus. All bits are ORed together to
generate the PCI interrupt. The sequence is:
• An AHB agent writes a pattern of ones to the PCI_PCIDOORBELL register, setting
the corresponding bits in the register.
• The interrupted PCI device reads the bit pattern in the doorbell register and writes
the same pattern back to clear the bits and deassert the interrupt.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
PCI CSR Read
23 16 15 7
8 0
2 1 0
16 15 7
8 0
AHB CSR Read
23 16 15 7
8 0
16 15 7
8 0
31 24
PCI Data
3
31 24 23
CSR
Register
31 24 23
CSR
Register
31 24 23
AHB Data
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
PCI CSR Write
23 16 15 8 7 0
2 1 0
16 15 8 7 0
AHB CSR Write
16 15 8 7 0
16 15 8 7 0
B4304-01
Develepor's Manual
547