Line Status Register - Intel IXP45X Developer's Manual

Universal Asynchronous Receiver-Transmitter (UART)—Intel
Product Line of Network Processors
Bits
2
1
0
14.5.10

Line Status Register

Register Name:
0xC800 X014
Hex Offset Address:
Register
Line Status Register
Description:
Access: Read Only.
31
Bits
31:8
7
6
5
August 2006
Order Number: 306262-004US
Register
Name
Test bit: This bit is used only in loop-back test mode.
OUT1
See LOOP row, above.
Request to Send: This bit controls the Request to Send (RTS_N) output pin.
RTS 0 = RTS_N pin is 1
1 = RTS_N pin is 0
Data Terminal Ready:
DTR 0 = DTR_N pin is 1
1 = DTR_N pin is 0
(Reserved)
Register
Name
(Reserved)
FIFO Error Status: In non-FIFO mode, this bit is 0. In FIFO Mode, FIFOE is set
to 1 when there is at least a parity error, framing error, or break indication for
any of the characters in the FIFO.
Note that a processor read to the Line Status register does not reset this bit.
FIFOE
FIFOE is reset when all error bytes have been read from the FIFO.
0 = Non-FIFO mode or no errors in receiver FIFO
1 = At least one character in receiver FIFO has errors
Transmitter Empty: TEMT is set to a logic 1 when the Transmit Holding
register and the Transmitter Shift register are both empty. It is reset to logic 0
when either the Transmit Holding register or the transmitter shift register
TEMT
contains a data character.
In FIFO mode, TEMT is set to 1 when the transmitter FIFO and the Transmit
Shift register are both empty.
Transmit Data Request: TDRQ indicates that the UART is ready to accept a
new character for transmission.
In Non-FIFO mode, The TDRQ bit is set to logic 1 when a character is
transferred from the Transmit Holding register into the Transmit Shift register.
The bit is reset to logic 0 concurrently with the loading of the Transmit Holding
TDRQ
register by the processor.
In FIFO mode, TDRQ is set to 1 when half of the characters in the FIFO have
been loaded into the Shift register or the RESETTF bit in FCR has been set to 1.
It is cleared when the FIFO has more than half data. If more than 64 characters
are loaded into the FIFO, the excess characters are lost.
Intel
® ®
IXP45X and Intel IXP46X
MCR
(Sheet 2 of 2)
Description
LSR
0x00000060
Reset Hex Value:
LSR
(Sheet 1 of 2)
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
8 7 6 5 4 3 2 1
BI FE
Developer's Manual
0
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