Timestamp Timer Operation - Intel IXP45X Developer's Manual

Operating System Timer—Intel
to these registers has no effect unless ost_wdog_key = key_value. This is to prevent
accidental writes to these registers. The typical operation would be for the software to
write the key-value into the ost_wdog_key register, write to the ost_wdog and/or
ost_wdog_enab, then the software would write a value other than key-value into the
ost_wdog_key register. It will then periodically (before the ost_wdog reaches zero)
write the key-value into the ost_wdog_key register, write a new count value into the
ost_wdog, then write a value other than the key-value into the ost_wdog_key register.
Upon reset the ost_wdog register is set to all ones, the ost_wdog_enab register is
disabled.
The ost_wdog_enab register contains three bits: wdog_cnt_ena, wdog_int_ena and
wdog_reset_n_ena. When enabled (by the wdog_cnt_ena bit) the ost_wdog
decrements. If it reaches zero it stops decrementing and drives a ost_wdog_int signal
and/or a ost_wdog_reset_n signal, depending on the values of wdog_int_ena and
wdog_reset_n_ena. These signals will continue to be driven active while the count in
the ost_wdog equals zero. If the ost_rst_enb bit is set, the entire chip will be reset
which will have the effect of setting all the OST registers to their initial state values as
described in the previous paragraph. If the wdog_rst_ena bit is not set a reset will not
occur. In this case the ost_wdog will remain zeros until software writes a different value
into it.
If the ost_wdog ever reaches zero when wdog_rst_en is enabled, the warm_reset
register bit is set. This register bit can be cleared by writing a '1' to it or by the
assertion of reset_cold_n which is derived from the Power On Reset.
18.4.2

Timestamp Timer Operation

The timestamp timer is a readable 32-bit free-running counter. Upon reset it is by
default set to 32'h0000_0001 and starts counting up as soon as reset is released.
Unless the timestamp compare register value is different from 32'h0000_0000, the
timer rolls over and generates an interrupt signal. The ost_ts_int signal is asserted until
cleared by a writing a 1'b1 to the appropriate bit in ost_sts register. If the compare
register has a different value than 32'h0000_0000, the timer generates an interrupt
when the timestamp counter equals the compare register value, the counter continues
to run. The ost_ts_int signal will stay asserted until cleared by writing a 1'b1 to the
appropriate bit in the ost_sts register. A prescale is activated by writing a value other
than 16'h0000 into the prescale value of the timestamp prescale register. The 3/4
scale_en is activated by writing a 1'b1 to ts_scale_en in the timestamp configuration
register. The timer can be paused by setting the ts_pause_en bit in the timestamp
configuration register. The timer can be restarted after a pause by clearing the
ts_pause_en bit. The Timestamp timer can only use the pause/restart feature if
prescale or 3/4scale_en is activated. When using the prescaler, the prescale register
needs updated before the counter is restarted to ensure the correct division rate. No
extra action is necessary if only the 3/4 scale is used (ts_scale_en is 1'b1 and
ost_ts_pre = 16'h0000).
Example:
Assume the ost_ts_pre register holds the value 16'h0001, and ts_scale_en is 1'b0. This
means the timestamp is counting with a APB clk divided by 2.
To pause the timer.
1. Set ts_pause_en to 1'b1.
When desirable to let the counter continue:
2. Refresh the ost_ts_pre register with a 16'h0001, then clear ts_pause_en.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Intel
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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