Intel IXP45X Developer's Manual page 266

Bits
31:5
4
3
2
1
0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
266
® ®
Intel IXP45X and Intel
Register
Name
(Reserved)
1 = Configures the MDC as an output clock.
Mdc_en Set to 1 for the IXP45X/IXP46X network processors MAC0 on NPE B.
This bit is set as Reserved for MACs on NPE A and NPE C
Send_jam 1 = Causes a jam sequence to be sent if reception of a packet begins.
Assertion ("1") causes the Transmit FIFO to be flushed. Data in the Transmit
clr_tx_err
FIFO is discarded.
Assertion ("1") causes the Receive FIFO to be flushed. Data in the Receive FIFO
clr_rx_err
is discarded.
rst_mac Assertion ("1") causes the MAC to be reset.
IXP46X Product Line of Network Processors—Ethernet MACs
core_control
Description
August 2006
Order Number: 306262-004US