Byte Lane Routing During Ahb Slave Accesses Of The Pci Bus; Little-Endian Ahb Bus - Intel IXP45X Developer's Manual

®
PCI Controller—Intel IXP45X and Intel
Figure 98. Byte Lane Routing During AHB Slave Accesses of the PCI Bus –

Little-Endian AHB Bus

31
24
PCI Data
3
31
24
AHB Data 11
31
24
PCI Data
3
31
24
AHB Data 11
During DMA transfers, byte lane routing is controlled by the DS bit in the DMA length
register as shown in
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
Write,
pci_csr.ADS = 1
23 16 15 7
8 0
2 0
1
23 16 15 7
8 0
10 00
01
Write,
pci_csr.ADS = 0
23 16 15 7
8 0
2 0
1
23 16 15 7
8 0
10 00
01
Figure 99.
31 24
PCI Data
3
31 24
AHB Data
11
31 24
PCI Data
3
31 24
AHB Data
11
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Read,
pci_csr.ADS = 1
23 16 15 8 7 0
2 1 0
23 16 15 8 7 0
10 01 00
Read,
pci_csr.ADS = 0
23 16 15 8 7 0
2 1 0
23 16 15 8 7 0
10 01 00
B4302-01
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