Mvip, Byte Interlacing Two E1 Streams Onto A 4.096-Mbps Backplane - Intel IXP45X Developer's Manual

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HSS Coprocessor—Intel IXP45X and Intel
Figure 180. MVIP, Byte Interlacing Two E1 Streams onto a 4.096-Mbps Backplane
4. 096
MHz clock
Frame pulse
6 7 0 1
Bits
Timeslots
31b 0a
0b 1a
In Figure
stream, the two streams are interlaced byte wise. Another method of placing E1 stream
on this backplane is to process the first entire E1 stream followed by the second
complete E2 stream (frame interleaving).
Figure 181
backplane. It can be seen that the first two timeslots are unassigned with the exception
of the frame pulse. The first three timeslots of each T1 stream are then placed
(interlaced) in succession on the bus, then one unassigned timeslot per T1 stream
present are placed on the bus. Unassigned RX bytes do not pass through the HSS FIFO
(lookup tables give unassigned timeslots).
The HSS can also transmit unassigned timeslots, the value of which is programmable.
The NPE Core need only supply the contents of the T1 frames, it does not need to
transmit unused timeslots to the HSS. The location of these unassigned timeslots are
defined by the lookup table.
The backplane can contain the 2 T1 streams byte interlaced as shown in
the T1 stream can be placed in its entirety first followed by eight unassigned timeslots
(frame pulse at the last bit of the 32
commences followed by eight unassigned timeslots. The frame pulse is coincidental
with the last bit in the 32
timeslot and together take up the 64 timeslots available. Once again the HSS can be
programmed by the NPE Core to ignore the eight unassigned timeslots while taking the
frame bit into account.
August 2006
Reference Number: 306262-004US
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IXP46X Product Line of Network Processors
2 3 4 5 6 7 0 1 2
3a
1b 2a 2b 3b 4a 4b 5a 5b
180, the 'a' denotes the first E1 stream, the 'b' denotes the second E1
illustrates a method in which two T1 frames are placed on a 4.096-Mbps
nd
timeslot. The second timeslot follows the format of the first
3 4 5 6 7 0 1 2 3
9a
6a 6b 7a 7b 8a 8b 9b 10a 10b 11a 11b 12a 12b 13a 13b 14a 14b 15a 15b
nd
timeslot. The second T1 stream then
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
4 5 6 7 0 1 2 3 4
Figure 181
Developer's Manual
5 6 7
16a
or
745