Hash Configuration Register; Hash Do Register - Intel IXP45X Developer's Manual

Table 292. Hashing Coprocessor: Register Summary (Sheet 2 of 2)
Block Offset
Register Name
Address Address
0x7000_ 2208
0x7000_ 220C
0x7000_ 2210
26.4.1

Hash Configuration Register

Register Name:
Block
0x7000_
Base Address:
Hashing Coprocessor Configuration Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
WEW REV WED RED
Register
Bits Name
31:3
WEW Set endianness for writing the chaining variables.
0
29:2
REV Set endianness for reading the chaining variables.
8
27:2
WED Set endianness for writing the data store.
6
25:2
RED Set endianness for reading the data variables.
4
23:1
(Reserved) These bits are always 0.
7
SHA-1 or MD5 mode select
16 MODE • 1 - MD-5
• 0 - SHA-1
15:0 (Reserved) These bits are always 0.
26.4.2

Hash Do Register

Register Name:
Block
0x7000_
Base Address:
Hashing Coprocessor Do Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
922
® ®
Intel IXP45X and Intel
Hash_Int Hash Interrupt Register
Hash_Chain Hash Chain Register
Hash_Data Hash Data FIFO
Offset Address
(Reserved)
Description
Offset Address
IXP46X Product Line of Network Processors—Hashing Unit (SHA)
Description
Hash_Config
2200
Hash_Config
Hash_Do
2204
(Reserved)
Page
Reset Value
Number
0x00000000 923
0x00000000 923
0x00000000 924
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3
(Reserved)
Reset
Value
0
0
0
0
0
0
0
N/A
Reset Value
Access: (See below.)
8 7 6 5 4 3
Reference Number: 0014US
Access
RW
RW
RW
2 1 0
Access
RW
RW
RW
RW
RW
RW
RW
2 1 0
DO
August 2006