Intel IXP45X Developer's Manual page 943

AHB Queue Manager (AQM)—Intel
Processors
Register Name:
Block
Reg #n 0x0420
Base Address:
Status Flag selection for interrupt 0 source on queues 0-31.
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Queue Queue
(8n + 7) (8n + 6)
Stat Src Stat Src
Sel Sel
Register
Bits Name
(0 <= k <= 7)
'b000: Queue (8n+k) Empty going TRUE
'b001: Queue (8n+k) Nearly Empty going TRUE
Status
'b010: Queue (8n+k) Nearly Full going TRUE
4k+2
Source
'b011: Queue (8n+k) Full going TRUE
:4k
Select
'b100: Queue (8n+k) Empty going FALSE
'b101: Queue (8n+k) Nearly Empty going FALSE
'b110: Queue (8n+k) Nearly Full going FALSE
'b111: Queue (8n+k) Full going FALSE
For INT0SRCSELREG0 (only), bit 3 is a configuration for the interrupt
operation. If bit 3 is a 0, its reset value, an interrupt bit will clear when
a 1 is written back to it in the QUEUEINTREG., even if the interrupting
condition is still true. If bit 3 is a 1, then interrupt bits will clear when
a 1 is written to QUEUEINTREG and the interrupting condition has
been satisfied. All 64 interrupts behave according to this bit.
The impact of this bit is shown in the following pseudo-code:
Clear
3
Interrupt
However, in one corner case, if INT0SRCSELREG0[3] == TRUE and
QUEINT0REG bits get set, if you then set INT0SRCSELREG0[3] ==
FALSE, the interrupt is generated even if the QUEIEREG bit
corresponding to a QUEINT0REG bit is FALSE. This occurs because of
the difference in the AQM_INT between the two cases.
August 2006
Reference Number: 306262-004US
®
IXP45X and Intel
Offset Address
Queue Queue
(8n + 5) (8n + 4)
Stat Src Stat Src
Sel Sel
Description
if (INT0SRCSELREG0[3] == FALSE) then
QUEINT0REG bits are set when the selected state change
happens AND the bit is enabled in the QUEIEREG register
QUEINT0REG bits are reset when the bit is written with a 1
AQM_INT is true if any QUEINT0REG bits are true
else
QUEINT0REG bits are set when the selected state change
happens
QUEINT0REG bits are reset when the bit is written with a 1 AND
the selected state is no longer true
AQM_INT is true if any (QUEIEREG AND QUEINT0REG) bits are
true
endif
®
IXP46X Product Line of Network
INT0SRCSELREG (0 <= n <=3)
+ 4n
Queue
(8n + 3) (8n + 2)
Stat Src Stat Src
Sel
INT0SRCSELREG (0 <= n <=3)
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3
Queue Queue
(8n + 1)
Stat Src
Sel Sel
Reset
Value
000
0
Developer's Manual
2 1 0
Queue (8n)
Stat Src
Sel
Access
RW
RW
943