Port Controller; Port Controller Block Diagram - Intel IXP45X Developer's Manual

Intel
• The CRC5 and CRC16 CRC generator/checker circuits check and generate the CRC
check fields for the token and data packets.
• The data and handshake state machines generate any responses required on the
USB and move the packet data through the dual port memory FIFOs to the DMA
controller block.
• The Interval timers provide timing strobes that identify important bus timing
events: the bus time-out interval, the microframe interval, the start of frame
interval, and the bus reset, resume, and suspend intervals.
• Reports all transfer status to the DMA engine.
9.6.3.6

Port Controller

The Port Controller block interfaces to the full-speed transceiver or any UTMI
compatible transceiver macro-cell core. The primary function of the Port Controller
block is to isolate the rest of the core from the transceiver and to move all of the
transceiver signaling into the primary clock domain of the USB core. This allows the
USB core to run synchronously with the system processor and its associated resources.
Figure 44.

Port Controller Block Diagram

Serial Xcvr
Parallel Xcvr
Aggregate
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
362
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Port Controller Serial Engine
Vusb_hs_portctrl_serial_engine.vhdl
DPLL NRZI
Clock Crossing &
Synchronization
Vusb_hs_rate_match
Rate Match/
Sychronization
Xcvr I/O
Registers
8/16 bit rate
conversion
Vusb_hs_rm_fifo
Asychronous
FIFO
6/10 stage 16-
bit wide FIFO
To
Microprocessor
Interface
Bit Parallel/Serial/
Stuff SYNC/EOP/etc
Vusb_hs_utmi_
char
UTMI
Xcvr
Logic
Vusb_hs_phil_
char
Philips
Xcvr
Logic
Vusb_hs_portctrl
_sm
Host Port
State
Machine
Device Port
State
Machine
Chirp
Control
Port Controller/
PE-TT Interface
Suspend/
Resume
Port Controller/
PE Interface
B4206-01
August 2006
Order Number: 306262-004US