Utopia Level 2; Introduction - Intel IXP45X Developer's Manual

7.0

UTOPIA Level 2

The functionality supported by the UTOPIA Level 2 interface is tightly coupled with the
code written on the Network Processor Engine (NPE). This chapter details the full
hardware capabilities of the UTOPIA Level 2 interface contained within the UTOPIA
Level 2 coprocessor of the Intel
Processors. The features accessible by the user are described in the Intel
Software Programmer's Guide and may be a subset of the features described in this
chapter.
Note: Not all of the IXP45X/IXP46X network processors have this functionality. For details,
see Intel
Manual.
7.1

Introduction

UTOPIA Level 2 is an industry-standard interface that is used to provide connection
between Asynchronous Transmission Mode (ATM) and physical layer (PHY) of an ATM
network. The UTOPIA Level 2 coprocessor is the entity within the IXP45X/IXP46X
network processors that provides the UTOPIA Level 2 interface.
The UTOPIA Level 2 coprocessor, implemented on the IXP45X/IXP46X network
processors, provides an 8-bit, UTOPIA Level 2 interface operating at speeds of up to
33 MHz. The UTOPIA Level 2 interface can be configured to operate in a single-PHY
(SPHY) or a multiple-PHY (MPHY) environment.
The interface contains five transmit and five receive address lines for multi-PHY
selection. The UTOPIA Level 2 coprocessor is comprised of three functional modules:
• UTOPIA Transmit Module
• UTOPIA Receive Module
• Network Processor Engine (NPE) Core Interface Module
Two 128-byte-deep FIFOs are contained in each direction of data flow — one FIFO for
transmit and one FIFO for receive. Each FIFO is organized into two cell buffers, each
being 64 bytes deep. This FIFO arrangement allows the receive module to be
processing a cell and storing it away at the same time the Network Processor Engine
core is processing a previously received cell.
In the transmit direction, the Network Processor Engine core can be placing a cell into
one transmit buffer while the Transmit Module is removing the cell from the other
transmit buffer.
When operating in single-PHY (SPHY) mode, the UTOPIA Level 2 interface will support
octet- or cell-level handshaking as defined by the UTOPIA Level 2 specification. When
configured in multiple-PHY (MPHY) mode, only cell-level handshaking is supported.
The hardware interface allows connection of up to 31 physical interface devices, as
defined in the UTOPIA Level 2 specification. However, the ATM Adaptation Layers (AAL)
supports only the following number of physical devices:
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
268
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Intel IXP45X and Intel
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IXP45X and Intel IXP46X Product Line of Network Processors Developer's
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IXP46X Product Line of Network Processors—UTOPIA Level 2
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IXP45X and Intel IXP46X Product Line of Network
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IXP400
August 2006
Reference Number: 306262-004US