National Microwire* Data Size (Mwds); Transmit Fifo Interrupt Threshold (Tft); Receive Fifo Interrupt Threshold (Rft); Enable Fifo Write/Read Function (Efwr) - Intel IXP45X Developer's Manual

Intel
Table 275. Motorola
SSP_S
CLK
SSP_S
FRM
SSP_T
XD4
SSP_R
XD4
20.5.2.6

National Microwire* Data Size (MWDS)

This bit sets the size of data in the Microwire format. If '1' a 16 bits data size is chosen
for the Microwire format, otherwise, an 8-bit data size.
20.5.2.7

Transmit FIFO Interrupt Threshold (TFT)

This 4-bit value sets the level at or below which the FIFO controller triggers a service
interrupt.
20.5.2.8

Receive FIFO Interrupt Threshold (RFT)

This 4-bit value sets the level at or above which the FIFO controller triggers a service
interrupt.
20.5.2.9

Enable FIFO Write/Read Function (EFWR)

This bit enables a special functional mode for the SSP. When EFWR = 0, then the SSP
operates in the normal mode described in this document. When EFWR = 1, then the
SSP enters a mode in which whenever the CPU reads or writes to the SSP Data register
it actually reads and writes exclusively to either the Transmit FIFO or the Receive FIFO
depending on the programmed state of the Select FIFO for EFWR (STRF) bit. In this
special mode, data will not be transmitted on the TXD pin and data input on the RXD
pin will not be stored. This mode can be used to test, through software, whether or not
the Transmit FIFO or the Receive FIFO operates properly as a first-in-first-out memory
stack.
20.5.2.10

Select FIFO for Enable FIFO Write/Read (STRF)

This bit selects whether the Transmit or Receive FIFO is enabled for writes and reads
whenever the EFWR is programmed to one, which puts the SSP in a special functional
mode.
Note: The following bit table shows bit locations corresponding to control bit fields in SSP
Control Register 1. Note that writes to reserved bits are ignored, and reads of these
bits return zero.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
868
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port
*
SPI Frame Formats for SPO and SPH Programming (Sheet 2 of 2)
SPO=1
Bit<N>
Bit<N>
MSB
...
...
Bit<N..> ... Bit<1> Bit<0>
Bit<N..> ... Bit<1> Bit<0>
4 to 16 Bits LSB
SPH = 1
August 2006
Order Number: 306262-004US