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Intel
Table 13.
Cache Type Register (Sheet 2 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
0
0
reset value: As Shown
Bits
5:3
2
1:0
3.5.1.2
Register 1: Control and Auxiliary Control Registers
Register 1 is made up of two registers, one that is compliant with Intel
Version 5TE and referred by opcode_2 = 0x0, and the other which is specific to the
Intel XScale processor is referred by opcode_2 = 0x1. The latter is known as the
Auxiliary Control Register.
The Exception Vector Relocation bit (bit 13 of the Intel
allows the vectors to be mapped into high memory rather than their default location at
address 0. This bit is readable and writable by software. If the MMU is enabled, the
exception vectors will be accessed via the usual translation method involving the PID
register (see
application of the PID to exception vector accesses, software may relocate the
exceptions to high memory.
®
Table 14.
Intel
StrongARM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:14
13
12
11
10
9
8
7
6:3
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
100
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—Intel XScale
0
1
0
1
1
0
0
0
Access
Read / Write Ignored
Read-as-Zero / Write Ignored
Read / Write Ignored
"Register 13: Process ID" on page
*
Control Register (Sheet 1 of 2)
Access
Read-Unpredictable /
Write-as-Zero
Read / Write
Read / Write
Read / Write
Read-as-Zero / Write-as-Zero
Read / Write
Read / Write
Read / Write
Read-as-One / Write-as-One
Dsize
1
0
1
0
1
0
Instruction cache associativity = 0b101 = 32-way
Reserved
Instruction cache line length = 0b10 = 8 words/line
106) and the TLBs. To avoid automatic
V
I
Reserved
Exception Vector Relocation (V).
0 = Base address of exception vectors is 0x0000,0000
1 = Base address of exception vectors is 0xFFFF,0000
Instruction Cache Enable/Disable (I)
0 = Disabled
1 = Enabled
Branch Target Buffer Enable (Z)
0 = Disabled
1 = Enabled
Reserved
ROM Protection (R)
This selects the access checks performed by the memory
management unit. See the ARM* Architecture Reference
Manual for more information.
System Protection (S)
This selects the access checks performed by the memory
management unit. See the ARM* Architecture Reference
Manual for more information.
Big- / Little-Endian (B)
0 = Little-endian operation
1 = Big-endian operation
= 0b1111
8
7
6
5
4
0
0
0
Isize
1
0
Description
®
StrongARM
®
*
StrongARM
control register)
8
7
6
5
4
Z
0
R S
B 1
1
1
Description
Order Number: 306262-004US
®
Processor
3
2
1
0
1
0
1
0
*
3
2
1
0
1
C
A M
August 2006
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