C Bus Configuration Example; Operational Blocks - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
2
Table 276. I C Bus Definitions (Sheet 2 of 2)
2
I C Device
Slave
Multi-master
Arbitration
As an example of I
processors acting as a master on the bus (see
addresses an EEPROM as a slave to receive data. The processor is a master-transmitter
and the EEPROM is a slave-receiver. When the processor reads data, it is a master-
receiver and the EEPROM is a slave-transmitter. In both cases, the master generates
the clock, initiates the transaction, and terminates it.
2
Figure 191. I

C Bus Configuration Example

2
The I C bus allows for a multi-master system, which means more than one device can
initiate data transfers at the same time. To support this feature, the I
relies on the wired-AND connection of all I
drive the bus simultaneously provided they are driving identical data. The first master
to drive SDA high while another master drives SDA low loses the arbitration. The SCL
line consists of a synchronized combination of clocks generated by the masters using
the wired-AND connection to the SCL line.
2
The I C bus serial operation uses an open-drain wired-AND bus structure, which allows
multiple devices to drive the bus lines and to communicate status about events such as
arbitration, wait states, error conditions and so on. For example, when a master drives
the clock (SCL) line during a data transfer, it transfers a bit on every instance that the
clock is high. When the slave is unable to accept or drive data at the rate that the
master is requesting, the slave can hold the clock line low between the high states to
insert a wait interval. The master's clock can only be altered by a slow slave peripheral
keeping the clock line low or by another master during arbitration.
2
I C transactions are either initiated by the IXP45X/IXP46X network processors as a
master or are received by the IXP45X/IXP46X network processors as a slave. Both
conditions may result in the processor doing reads, writes, or both to the I
21.4.1

Operational Blocks

2
The I C Bus Interface Unit is a slave peripheral device that is connected to the
peripheral bus. The interrupt mechanism for the IXP45X/IXP46X network processors
can be used for notifying the CPU that there is activity on the I
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IXP45X and Intel IXP46X Product Line of Network Processors
The device addressed by a master.
More than one master can attempt to control the bus at the same time without corrupting
the message.
Procedure to ensure that, when more than one master simultaneously tries to control the
bus, only one is allowed. This procedure ensures that messages are not corrupted.
2
C bus operation, consider the case of the IXP45X/IXP46X network
Intel® IXP46X
Network Processor
SCL
SDA
Gate
Array
Definition
Figure 191). The processor, as a master,
EEPROM
Micro-
Controller
B4255-02
2
C interfaces to the I
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
2
C bus arbitration
2
C bus. Two masters can
2
C bus.
2
C bus. Polling can be
Developer's Manual
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