Ecc Test Register Ectst - Intel IXP45X Developer's Manual

®
Memory Controller—Intel
11.6.10

ECC Test Register ECTST

This register allows testing between the ECC logic and the memory subsystem
Testing" on page
register with a non-zero masking function. Any subsequent writes to memory stores a
masked version of the computed ECC. Therefore, any subsequent reads to these
locations result in an ECC error.
Register Name:
Hex Offset Address:
Register Description:
Access: See below.
31
Register
Bits Name
31:0
(Reserved)
8
ECC Mask: 8-bit ECC mask. Each bit of the generated ECC is XORed
07:0
with the appropriate bit in this mask field before the ECC is stored into
0
memory. See
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
625). To test error handling software, the programmer writes this
CC00 E530H
ECC Test Register
(Reserved)
Description
"ECC Testing" on page
ECC Test Register - ECTST
Reset Hex Value:
ECC Test Register - ECTST
625.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
("ECC
0x0000 0000H
08 07
Default Access
00 0000H RO
00H RW
Developer's Manual
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