Usbsts - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
Table 134. USBCMD – USB Command Register (Sheet 2 of 2)
Field
PSE
FS[2:0]
RST
RS
9.12.2

USBSTS

Address:
Default Value: 0x00001000 (host mode)
Attribute:
Size:
This register indicates various states of the Host Controller and any pending interrupts.
This register does not indicate status resulting from a transaction on the serial bus.
Software clears certain bits in this register by writing a 1 to them.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Periodic Schedule Enable— Read/Write. Default Ob. This bit controls whether the host
controller skips processing the Periodic Schedule.
Values meaning
0 Do not process the Periodic Schedule
1 Use the PERIODICLISTBASE register to access the Periodic Schedule.
Only the host controller uses this bit.
Frame List Size — (Read/Write or Read Only).
Default 000b. This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS
registers is set to one. This field specifies the size of the frame list that controls which bits in
the Frame Index Register should be used for the Frame List Current index. Note that this field
is made up from USBCMD bits 15, 3 and 2.
Values meaning
000 1024 elements (4096 bytes) Default value
001 512 elements (2048 bytes)
010 256 elements (1024 bytes)
011 128 elements (512 bytes)
100 64 elements (256 bytes)
101 32 elements (128 bytes)
110 16 elements (64 bytes)
111 8 elements (32 bytes)
Only the host controller uses this field.
Controller Reset (RESET) — Read/Write. Software uses this bit to reset the controller. This
bit is set to zero by the Host Controller when the reset process is complete. Software cannot
terminate the reset process early by writing a zero to this register.
Host Controller:
When software writes a one to this bit, the Host Controller resets its internal pipelines, timers,
counters, state machines etc. to their initial value. Any transaction currently in progress on
USB is immediately terminated. A USB reset is not driven on downstream ports. Software
should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.
Attempting to reset an actively running host controller will result in undefined behavior.
Run/Stop (RS) – Read/Write.
Default 0b.
0 = Stop.
1 = Run.
Host Controller:
When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host
Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the
Host Controller completes the current transaction on the USB and then halts. The HC Halted
bit in the status register indicates when the Host Controller has finished the transaction and
has entered the stopped state. Software should not write a one to this field unless the host
controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one).
Base + 144h
Read Only, Read/Write, Read/Write-Clear (field dependent)
32 bits
Intel
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
375