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USB 2.0 Host Controller—Intel
9.5
Block Diagram
Figure 37
CPU is the Intel XScale
memory the USB block has its DMA engine pointed to. In this case, note that the USB
2.0 compliance is restricted to a legacy full-speed protocol and that the system
memory is restricted to Memory Controller Unit accesses only.
Figure 37.
Top-Level Block Diagram
System CPU
Device Stack
9.6
Theory of Operation
9.6.1
Software Model
The Host Stack provides a layered software architecture to control all aspects of a USB
bus system. The Host Controller Device (HCD) interface controls the functions of an
embedded EHCI host controller. The USB driver layer provides all the USB driver
functions to enumerate, manage and schedule a USB bus system, while the upper
layers of the stack support standard USB device class interfaces to the device drives
running on your embedded system. Detailed information can be obtained by referring
to the USB 2.0 specification located at www.usb.org.
9.6.2
Host Data Structure
The host data structures are used to communicate control, status, and data between
software and the Host Controller. The Periodic Frame List is an array of pointers for
the periodic schedule. A sliding window on the Periodic Frame List is used. The
Asynchronous Transfer List is where all the control and bulk transfers are managed.
The Host API incorporates and abstracts for the application developer all of the
information contained in the host operational model.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
shows the top-level block diagram for the module. In this case, the system
®
Processor and the system memory is whatever system
AHB System Bus
System
Memory
Transfer
Descriptors
Endpoint Data
DMA Engine
Latency Buffers
Full-Speed
Protocol Engine
Xcvr Interface
USB 2.0 LS/FS
Transceiver
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
USB Host
B3976-001
Developer's Manual
355
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