Write 2 Bytes And Repeated Start Read 1 Byte As A Master; Read 2 Bytes As A Master — Send Stop Using The Abort - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
21.7.4

Write 2 Bytes and Repeated Start Read 1 Byte as a Master

1. Write IDBR: Target slave address and R/W# bit (0 for write).
2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the
access.
3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:
Read status register: IDBR Transmit Empty (1), Unit busy (1), R/W# bit (0).
4. Clear IDBR Transmit Empty bit to clear the interrupt.
5. Load data byte to be transferred in the IDBR.
6. Initiate the write
Write ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Set Transfer
Byte bit.
7. Wait for Buffer empty interrupt.
Read status register: IDBR Transmit Empty (1), Unit busy (1), R/W# bit (0).
8. Clear IDBR Transmit Empty bit to clear the interrupt.
9. Repeat steps 5-8 one time.
10. Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.
11. Send repeated start as a master.
Write ICR: Clear START bit, Clear STOP bit, clear ICR[ALDIE], Set Transfer Byte bit
to initiate the access.
12. Wait for Buffer empty interrupt.
Read status register: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (1).
13. Clear IDBR Transmit Empty bit to clear the interrupt.
14. Initiate the read.
Write ICR: Clear START bit, Set STOP bit, set ICR[ALDIE], Set Ack/Nack bit (Nack),
Set Transfer Byte bit to initiate the access.
15. Wait for Buffer full interrupt. When interrupt comes (Note: Unit will be sending
STOP).
Read status register: IDBR Receive Full (1), Unit busy (x), R/W# bit (1), Ack/Nack
bit (1).
16. Clear IDBR Receive Full bit to clear the interrupt.
17. Read IDBR data.
18. Clear ICR STOP bit (optional), Clear ICR Ack/Nack Control bit (optional).
21.7.5 Read 2 Bytes as a Master — Send STOP Using the Abort
1. Write IDBR: Target slave address and R/W# bit (1 for read).
2. Write ICR: Set START bit, Clear STOP bit, Disable Arb loss interrupt, Set Transfer
Byte bit to initiate the access.
3. Wait for IDBR Transmit Empty interrupt. When interrupt comes.
Read status register: IDBR Transmit Empty (1), Unit Busy (1), R/W# bit (1)
Clear IDBR Transmit Empty bit to clear the interrupt.
4. Read byte 1.
Write ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Clear Ack/
Nack bit (Ack), Set Transfer Byte bit to initiate the access.
5. Wait for Buffer full interrupt.
Read status register: IDBR Receive Full (1), Unit busy (1), R/W# bit (1), Ack/Nack
bit (0)
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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