Intel Synchronous 8-Word Read - Intel IXP45X Developer's Manual

12.4.1.8.5 Synchronous Intel 8-Word Read Access
Figure 133. Intel Synchronous 8-Word Read
T
- 0 - - 1 -
EX_ CLK
EX_CS_N
EX_ ADDR
ADDR0
EX_ ALE
EX_RD_N
EX_WR_N
EX_BE_N
EX_ IOWAIT _N
EX_ DATA
EX_ PARITY
STATE
IDLE ADDRESS
The above timing diagram shows an 8-word read to a Synchronous Intel device such as
Synchronous Intel StrataFlash. Depending on the EX_CLK period, the latency count bits
in the Intel Synchronous Device read configuration register needs to be programmed
appropriately. The Expansion bus controller will always wait in cycles 1 and 2,
regardless of EX_IOWAIT_N.
cycles and deassert EX_IOWAIT_N when its ready to transfer data. After the device
deasserts EX_IOWAIT_N, it will transfer the remaining words until all 8 words are
transferred. The Expansion bus controller and Synchronous Intel device both support
wrapping for 8-word reads, therefore ADDR0 is not always aligned to an 8-word
boundary. The STATE signal shows the internal Expansion bus state.
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- 2 - - 3 - - 4 - - 5 -
DATA0 DATA1
PAR0 PAR1
WAIT WAIT DATA0 DATA1
The device will then assert EX_IOWAIT_N for several
IXP46X Product Line of Network Processors—Expansion Bus
- 6 - - 7 - - 8 - - 9 -
DATA2 DATA3 DATA4 DATA5
PAR2 PAR3 PAR4 PAR5
DATA2 DATA3 DATA4 DATA5
Controller
- 10 - - 11 - - 12 - - 13 -
DATA6 DATA7
PAR6 PAR7
DATA6 DATA7 IDLE
B4400-01
August 2006
Order Number: 306262-004US