Saturated Arithmetic Instructions; Status Register Access Instructions; Load/Store Instructions; Multiply Implicit Accumulate Instruction Timings - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Table 85.

Multiply Implicit Accumulate Instruction Timings

Mnemonic
MIA
MIAxy
MIAPH
Table 86.

Implicit Accumulator Access Instruction Timings

Mnemonic
MAR
MRA
† If the next instruction needs to use the result of the MRA for a shift by immediate or as Rn in a
QDADD or QDSUB, one extra cycle of result latency is added to the number listed.
3.9.4.5

Saturated Arithmetic Instructions

Table 87.

Saturated Data Processing Instruction Timings

h
Mnemonic
QADD
QSUB
QDADD
QDSUB
3.9.4.6

Status Register Access Instructions

Table 88.

Status Register Access Instruction Timings

Mnemonic
MRS
MSR
3.9.4.7

Load/Store Instructions

Table 89.

Load and Store Instruction Timings

Mnemonic
LDR
LDRB
LDRBT
LDRD
LDRH
LDRSB
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Rs Value (Early Minimum Issue
Termination)
Rs[31:15] = 0x0000
or
Rs[31:15] = 0xFFFF
Rs[31:27] = 0x0
or
Rs[31:27] = 0xF
all others
N/A
N/A
Minimum Issue Latency
2
1
Minimum Issue Latency
1
1
1
1
Minimum Issue Latency
1
2 (6 if updating mode bits)
Minimum Issue Latency
1
1
1
1 (+1 if Rd is R12)
1
1
Intel
Minimum Result
Latency Latency
1 1
1 2
1 3
1 1
1 2
Minimum Result Latency
2
†
(RdLo = 2; RdHi = 3)
Minimum Result Latency
Minimum Result Latency
Minimum Result Latency
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
1 (+1 if Rd is R12) for write-back of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Minimum Resource
Latency
(Throughput)
1
2
3
1
2
Minimum Resource
Latency (Throughput)
2
2
2
2
2
2
2
1
3 for Rd; 4 for Rd+1;
Developer's Manual
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