Auxiliary Master Mode Snapshot Low Register – Amms_Low; Auxiliary Master Mode Snapshot High Register – Amms_High - Intel IXP45X Developer's Manual

Network processors
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Time Synchronization Hardware Assist (TSYNC)—Intel
Line of Network Processors
19.5.2.14
Auxiliary Master Mode Snapshot Low Register – AMMS_Low
Register Name:
Block
RegBlockAddress
Base Address:
Auxiliary Master Mode Snapshot Low Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
When the board is operating in Master mode, it receives a general-purpose
input signal for synchronization of snapshots and time. This general-purpose
input, ammssig, is synchronized by the system clock in the Time Sync logic
before it is used.
Note: The processor can configure the GPIO as an output, but it will always be
31:0
AMMS_Low
an input-only to the Time Sync block.
When the AMMS snapshot occurs, the snm indication in the Time Sync Event
register is asserted. No new snapshots in the AMMS register pair are captured
until the firmware writes a '1' back to the snm bit to clear the snapshot
indication.
Auxiliary Master Mode Snapshot High Register – AMMS_High
19.5.2.15
Register Name:
Block
RegBlockAddress
Base Address:
Auxiliary Master Mode Snapshot High Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
When the board is operating in Master mode, it receives a general-purpose
input signal for synchronization of snapshots and time. This general-purpose
input, ammssig, is synchronized by the system clock in the Time Sync logic
before it is used.
Note:
31:0
AMMS_High
When the AMMS snapshot occurs, the snm indication in the Time Sync Event
register is asserted. No new snapshots in the AMMS register pair are captured
until the firmware writes a '1' back to the snm bit to clear the snapshot
indication.
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
Offset Address
AMMS_Low[31:0]
Description
Offset Address
AMMS_High[31:0]
Description
The processor can configure the GPIO as an output, but it will always
be an input-only to the Time Sync block.
Intel
®
IXP46X Product
TS_AMMSLo
0x038
TS_AMMSLo
TS_AMMSHi
0x03C
TS_AMMSHi
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
0x0
Reset Value
Access:
(See below.)
8
7
6
5
4
3
2
Reset
Access
Value
0
0x0
Reset Value
Access:
(See below.)
8
7
6
5
4
3
2
Reset
Access
Value
0
Developer's Manual
1
0
RO
1
0
RO
847

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