Intel IXP45X Developer's Manual page 17

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Contents-Intel IXP45X and Intel
11.2.1.2 Address Decode Blocks ............................................................ 585
11.2.1.3 Memory Transaction Queues .................................................... 586
11.2.1.4 Configuration Registers............................................................ 586
11.2.1.5 Refresh Counter ..................................................................... 586
11.2.1.6 DDRI SDRAM Control Block ...................................................... 587
11.2.1.7 DDRI SDRAM RCOMP Block ...................................................... 587
11.2.2 DDRI SDRAM Memory Support ............................................................... 587
11.2.2.1 DDRI SDRAM Interface ............................................................ 588
11.2.2.2 DDRI SDRAM Bank Sizes and Configurations .............................. 590
11.2.2.3 MTCTR Register Setup ............................................................. 593
11.2.2.4 DDRI SDRAM Addressing ......................................................... 593
11.2.2.5 32-Bit Data Bus Width ............................................................. 594
11.2.2.6 Page Hit/Miss Determination .................................................... 595
11.2.2.7 DDRI SDRAM Commands ......................................................... 598
11.2.2.8 DDRI SDRAM Initialization........................................................ 598
11.2.2.9 DDRI SDRAM Mode Programming.............................................. 602
11.2.2.10DDRI SDRAM Read Cycle ......................................................... 606
11.2.2.11DDRI SDRAM Write Cycle ......................................................... 609
11.2.2.12DDRI SDRAM Refresh Cycle...................................................... 612
11.2.3 Error Correction and Detection ............................................................... 614
11.2.3.1 ECC Generation ...................................................................... 615
11.2.3.2 ECC Generation for Partial Writes .............................................. 617
11.2.3.3 ECC Checking......................................................................... 620
11.2.3.4 Scrubbing .............................................................................. 624
11.2.3.5 ECC Disabled.......................................................................... 625
11.2.3.6 ECC Testing ........................................................................... 625
11.2.4 Overlapping Memory Regions ................................................................. 626
11.2.5 DDRI SDRAM Clocking .......................................................................... 626
11.2.6 Performance Monitoring ........................................................................ 626
11.3 Power Failure Mode ......................................................................................... 627
11.4 Interrupts/Error Conditions ............................................................................... 627
11.4.1 Single-Bit Error Detection ...................................................................... 628
11.4.2 Multi-Bit Error Detection........................................................................ 629
11.5 Reset Conditions ............................................................................................. 629
11.6 Register Definitions ......................................................................................... 630
11.6.1 DDRI SDRAM Initialization Register SDIR................................................. 632
11.6.2 DDRI SDRAM Control Register 0 SDCR0 .................................................. 633
11.6.3 DDRI SDRAM Control Register 1 SDCR1 .................................................. 635
11.6.4 DDRI SDRAM Base Register SDBR .......................................................... 637
11.6.5 DDRI SDRAM Boundary Register 0 SBR0 ................................................. 638
11.6.6 DDRI SDRAM Boundary Register 1 SBR1 ................................................. 639
11.6.7 ECC Control Register ECCR .................................................................... 640
11.6.8 ECC Log Registers ELOG0, ELOG1........................................................... 641
11.6.9 ECC Address Registers ECAR0, ECAR1..................................................... 642
11.6.10ECC Test Register ECTST....................................................................... 643
11.6.11Memory Controller Interrupt Status Register MCISR .................................. 644
11.6.12MCU Port Transaction Count Register MPTCR............................................ 645
11.6.13MCU Preemption Control Register MPCR .................................................. 645
11.6.14Refresh Frequency Register RFR ............................................................. 646
11.6.15SDRAM Page Registers SDPR0-7............................................................. 647
12.0 Expansion Bus Controller ....................................................................................... 649
12.1 Overview ....................................................................................................... 649
12.2 Feature List .................................................................................................... 649
12.3 Block Diagram ................................................................................................ 650
12.4 Theory of Operation......................................................................................... 650
12.4.1 Outbound Transfers .............................................................................. 650
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
17