Using The Modem Control Signals - Intel IXP45X Developer's Manual

Intel
14.4.3

Using the Modem Control Signals

The IXP45X/IXP46X network processors provide two modem control signals, the Clear-
to-Send input (CTS_N) and the Ready to Send output (RTS_N).
The Clear-to-Send input signal is sampled by reading the Modem Status Register and
the Ready-to-Send output is controlled by the Modem Control Register. The Modem
Control Register is a 5-bit register that provides control for four modem control signals:
• OUT1
• Ready-to-Send
Only one of the four modem-control signals (Ready-to-Send) is replicated to the
external pins of the IXP45X/IXP46X network processors. The three other modem-
control signals are only utilized when the UART is being used in loop-back diagnostic
mode. Bit 4 of the Modem-Control Register is the Loop Back Test Mode bit (LOOP). The
Loop Back Test Mode bit provides a local loop-back feature for diagnostic testing of the
UART.
When the Loop Back Test Mode bit is set to logic 1, the following event will occur:
• The transmitter serial output is set to logic-1 state.
• The receiver serial input is disconnected from the pin.
• The output of the Transmitter Shift Register is "looped back" into the Receiver Shift
Register input.
• The Clear-to-Send input signal is disconnected from the pin
• The Ready-to-Send output signal is forced to logic 1.
• The lower four bits of the Modem Control Register are connected to the upper four
bits of the Modem Status Register
Status register bit mapping, while in loop back mode:
— DTR = 1 forces DSR to a 1
— RTS = 1 forces CTS to a 1
— OUT1 = 1 forces RI to a 1
— OUT2= 1 forces DCD to a 1
Leaving loop-back mode and returning to normal mode may result in unpredictable
activation of the Modem Status Register (MSR). It is recommended that the Modem
Status Register be read once to clear the Modem Status Bits in the Modem Status
Register.
In the loop-back diagnostic mode, data that is transmitted will be immediately
received. The ability to loop back the transmit data path to the receive path allows the
Intel XScale processor to verify the transmit data path and receive data path of the
UART. The transmit interrupts, receive interrupts, and modem-control interrupts are
operational, when placed in the loop-back diagnostic mode. The Modem-Control
Register Bits — instead of the Modem Control inputs — will activate the modem-control
interrupts. A break signal can also be transferred — from the transmitter section to the
receiver section — while operating in loop-back diagnostic mode.
Bit 1 of the Modem-Control Register is the Request-to-Send Bit. The Request-to-Send
Control Bit is used to program the RTS_N output pin. When the Request-to-Send
control bit is programmed to logic 0, the RTS_N signal will output logic 1. When the
Request-to-Send Control Bit is programmed to logic 1, the RTS_N signal will output
logic 0.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
756
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous
• OUT2
• Loop-back test control
bit
Receiver-Transmitter (UART)
• Data Terminal Ready
August 2006
Order Number: 306262-004US