Ipv6 Compatibility; Traffic Analyzer Support; Mii Clocking Methods; System Time Clock Rate Set By Addend Register - Intel IXP45X Developer's Manual

Time Synchronization Hardware Assist (TSYNC)—Intel
Line of Network Processors
Delay_Req Message
19.3.4
Firmware in a time slave can transmit a Delay_Req message to the master for the
purpose of determining propagation delays in the network. A Delay_Req message is
defined as a value of 0x01 in byte 74 of the Ethernet frame after the start of frame
delimiter.
The TSync logic will monitor the MII signals, detect when the channel has transmitted
or received a Delay_Req message, and lock the timestamp. Furthermore, the TSync
logic captures the Sequence ID and Source UUID if a Sync message is received by a
channel configured as a time master.
Delay_Resp Message
19.3.5
Upon receipt of a Delay_Req message, firmware in a time master will transmit a
Delay_Resp message that includes the timestamp of the Delay_Req message it
received. No time stamping is done with the Delay_Resp message itself. A Delay_Resp
message is defined with a value of 0x03 in byte 74 of the Ethernet frame after the start
of frame delimiter.
The 1588 standard uses UDP/IP protocol, which implies that messages can be lost.
Because a Delay_Req message can be locked out until firmware in the master channel
enables it, the slave channel firmware will have to retry sending the Delay_Req
message to the master if the slave does not receive a Delay_Resp message within
some timeout period.

IPv6 Compatibility

19.3.6
A time sync message is always defined using an IPv4 message format. To avoid the
potential of mistaking an IPv6 packet with a time sync packet, the byte at offset 14 will
be checked for a value of 0x45. If not 0x45, the packet will be ignored. IPv6 is not
supported

Traffic Analyzer Support

19.3.7
In a traffic analyzer type application, it is often desirable to timestamp every message
on the network. An optional mode inhibits the "locking" of the time snapshot so that
the SFD of every message triggers a time snapshot. In this mode the snapshot must be
read (presumably by the NPE) during the message before the next SFD is received.
19.3.8

MII Clocking Methods

According to the IEEE 802.3 specification, the MII TX/RX data transitions synchronously
with the MII clock (rising edge is implied). For the TX case, txclk is driven by the PHY,
but txdata is driven by MAC. The txdata bus transitions some time after rising edge of
txclk and is sampled at next rising edge by the PHY. For the RX case, the PHY drives
rxclk and rxdata. The rxdata bus transitions on the falling edge of rxclk to provide
sufficient setup time for the MAC to sample at next rising edge. The characteristics of
the MII in cases of transmit and receive should be taken into consideration when
constraining the design for synthesis.
19.3.9

System Time Clock Rate Set by Addend Register

The FreqOscillator is the frequency of all portions of the frequency compensated clock,
or time synchronization circuit. The frequency compensation value
(FreqCompensationValue) is the number held in the Addend register, which is added to
the accumulator once every 1/FreqOscillator. To determine the value that should be
placed in the Addend register, the following equation is used:
August 2006
Order Number: 306262-004US
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