Mvip; Gci Frames, Internally Generated Frame Pulse (Termination Mode) - Intel IXP45X Developer's Manual

Figure 177. GCI Frames, Internally Generated Frame Pulse (Termination Mode)
hss_tx_clock
7
hss_rx_data /
hss_tx_data_out
hss_tx_frame _out
8 KHz frame pulse
The clock runs at 0.768 MHz, unlike other GCI protocols the clock rate is equal the data
rate.
The following settings should be used when programming the HSS for GCI,
• Set frame size for GCI.
• Frame sync simultaneous with first bit – set TX frame offset and RX frame offset set
to due to HSS logic, different values due to external device can be accommodated.
• Select use of input/output TX/RX frame syncs.
• Select use of input/output clock, and clock speed.
• Select negative/positive clock for generating/sampling frame in transmit/receive.
• Select negative/positive clock for generating/sampling data in transmit/receive.
• Frame sync active level (high/low).
• MSb/LSb-first ordering for transmit and receive.
• Data polarity, maintain or invert.
• Select to not use FBit in the frame.
• Select value for idle timeslots on transmit.
• Configure buffer size.
13.5.4

MVIP

MVIP provides a method of interlacing E1 streams onto a single E1 line, and multiple T1
streams onto a single T1 line. Increasing the clock speed and alternating various
timeslots helps provide this functionality. A single T1 line can also be mapped into an
E1 line.
The NPE Core can program the HSS in the following ways.
Consider the following when programming the HSS for MVIP:
• Set frame size for MVIP.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
742
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Intel IXP45X and Intel
subframe 0 subframe 1
3 2
6 5 4 1 0
Channel 0 Channel 1
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IXP46X Product Line of Network Processors—HSS Coprocessor
subframe 2
7 6 5 4 3 2 1 0
Channel 2
subframe 3
B4248-02
August 2006
Reference Number: 004US