Tx Frame Sync Example (Presuming Zero Offset) - Intel IXP45X Developer's Manual

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HSS Coprocessor—Intel IXP45X and Intel
The HSS will not request data from the NPE Core until it has synced up to the TX frame
pulse. Meaning that the HSS must detect two consecutive frame pulses (in the case of
gapped frame pulses, then sync is assumed on the detection of the second frame
pulse). Once data has been sent from the NPE Core, the data will be transmitted at the
start of the next frame. If an offset is programmed, the data transmitted will be
transmitted the offset number of clock cycles before the frame pulse.
If the HSS core has not synchronized to the frame pulse, it will not request TX/RX
servicing nor will it indicate under/overflow conditions. Data received before
synchronization is lost, regardless of what caused the loss of sync (reset/frame pulse
error/incorrect programming, and so on), will be dropped. When not synchronized, the
TX data pin is set to high impedance.
If under-run/over-run occurs, frame sync is maintained if the frame pulse is still
generated (if sourced either internally or externally).
The behavior of the HSS is indifferent to the source of the frame pulse (in terms of
synchronization), be it sourced externally or generated internally.
Figure 168. TX Frame Sync Example (Presuming Zero Offset)
hss_tx_clock
hss_tx_frame _out_en
hss_tx_frame_out
hss_tx_data_out_en
hss_tx_data_out
August 2006
Reference Number: 306262-004US
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IXP46X Product Line of Network Processors
Correct interval
®
Intel IXP45X and Intel
Correct interval
data
Data from here will
be transmitted
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IXP46X Product Line of Network Processors
data
B4236-02
Developer's Manual
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