Write 1 Byte As A Master; Read 1 Byte As A Master; Master Programming Examples - Intel IXP45X Developer's Manual

Intel
21.7

Master Programming Examples

21.7.1 Initialize Unit
1. Write ISAR: Set slave address.
2. Write ICR: Enable all interrupts (except Arb Loss), set SCL Enable, set Unit Enable
and enable the I
21.7.2

Write 1 Byte as a Master

1. Write IDBR: Target slave address and R/W# bit (0 for write).
2. Write ICR: Set START bit, Clear STOP bit, clear ICR[ALDIE], Set Transfer Byte bit to
initiate the access.
3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:
Read status register: IDBR Transmit Empty (1), Unit Busy (1), R/nW bit (0).
4. Clear IDBR Transmit Empty Interrupt bit to clear the interrupt.
5. Write a 1 to the ISR[ALD] bit if set.
If the master loses arbitration, it performs an address retry when the bus becomes
free. The Arbitration Loss Detection interrupt is disabled to allow the address retry.
6. Load data byte to be transferred in the IDBR.
7. Write ICR: Clear START bit, Set STOP bit, Enable Arb Loss interrupt, Set Transfer
Byte bit to initiate the access.
8. Wait for Buffer empty interrupt. When interrupt arrives (Note: Unit will be sending
STOP):
Read status register: IDBR Transmit Empty (1), Unit busy (x), R/nW bit (o).
9. Clear IDBR Transmit Empty Interrupt bit to clear the interrupt.
10. Clear ICR STOP bit.
21.7.3

Read 1 Byte as a Master

1. Write IDBR: Target slave address and R/W# bit (1 for read).
2. Write ICR: Set START bit, Clear STOP bit, Disable Arb loss interrupt, Set Transfer
Byte bit to initiate the access.
3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:
Read ISR: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (1).
4. Clear IDBR Transmit Empty bit to clear the interrupt.
5. Read byte with STOP
Write ICR: Clear START bit, Set STOP bit, Enable arb loss interrupt, Set Ack/Nack
bit (Nack), Set Transfer Byte bit to initiate the access.
6. Wait for Buffer full interrupt. When interrupt arrives (Note: Unit will be sending
STOP):
Read status register: IDBR Receive Full (set), Unit Busy (set - maybe), R/W# bit
(Set), Ack/Nack bit (Set).
7. Clear IDBR Receive Full bit to clear the interrupt.
8. Read IDBR data.
9. Clear ICR STOP bit (optional), Clear ICR Ack/Nack Control bit (optional).
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
894
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IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
2
C.
August 2006
Order Number: 306262-004US