Periodic Schedule - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
Table 172. Operation of FRINDEX and SOFV (SOF Value Register) (Sheet 2 of 2)
N+1
N+1
N+1
Note: Where [F] = [13:3]; [μF] = [2:0]
9.14.6

Periodic Schedule

The periodic schedule traversal is enabled or disabled via the Periodic Schedule Enable
bit in the USBCMD register. If the Periodic Schedule Enable bit is set to a zero, then the
host controller simply does not try to access the periodic frame list via the
PERIODICLISTBASE register. Likewise, when the Periodic Schedule Enable bit is a one,
then the host controller does use the PERIODICLISTBASE register to traverse the
periodic schedule. The host controller will not react to modifications to the Periodic
Schedule Enable immediately. In order to eliminate conflicts with split transactions, the
host controller evaluates the Periodic Schedule Enable bit only when FRINDEX[2:0] is
zero. System software must not disable the periodic schedule if the schedule contains
an active split transaction work item that spans the 000b micro-frame. These work
items must be removed from the schedule before the Periodic Schedule Enable bit is
written to a zero. The Periodic Schedule Status bit in the USBSTS register indicates
status of the periodic schedule. System software enables (or disables) the periodic
schedule by writing a one (or zero) to the Periodic Schedule Enable bit in the USBCMD
register. Software then can poll the Periodic Schedule Status bit to determine when the
periodic schedule has made the desired transition. Software must not modify the
Periodic Schedule Enable bit unless the value of the Periodic Schedule Enable bit equals
that of the Periodic Schedule Status bit.
The periodic schedule is used to manage all isochronous and interrupt transfer streams.
The base of the periodic schedule is the periodic frame list. Software links schedule
data structures to the periodic frame list to produce a graph of scheduled data
structures. The graph represents an appropriate sequence of transactions on the USB.
Figure 59, "Example Periodic Schedule" on page 426
(using iTDs and siTDs) with a period of one are linked directly to the periodic frame list.
Interrupt transfers (are managed with queue heads) and isochronous streams with
periods other than one are linked following the period-one iTD/siTDs. Interrupt queue
heads are linked into the frame list ordered by poll rate. Longer poll rates are linked
first (e.g. closest to the periodic frame list), followed by shorter poll rates, with queue
heads with a poll rate of one, on the very end.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Current
N+1 100b
N+1 101b
N+1 110b
Intel
N+1
N+1
N+1
illustrates isochronous transfers
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Next
N+1 101b
N+1 110b
N+1 111b
Developer's Manual
425