Udc Data Register 5; Udc Data Register 6 - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
8.5.35

UDC Data Register 5

Endpoint 5 is an interrupt IN endpoint that is 8 bytes deep. Data must be loaded via
direct Intel XScale processor writes.
Because the USB system is a host-initiator model, the host must poll Endpoint 5 to
determine interrupt conditions. The UDC cannot initiate the transaction.
Register Name:
0 x C800B008
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 5 Data Register
Description:
Access: Write.
31
Bits
31:8
7:0
8.5.36

UDC Data Register 6

Endpoint 6 is a double-buffered, bulk IN endpoint that is 64 bytes deep. Data can be
loaded via direct Intel XScale processor writes.
Because it is double-buffered, up to two packets of data may be loaded for
transmission.
Register Name:
0 x C800B600
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 6 Data Register
Description:
Access: Write
31
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being loaded.
Bits
(Reserved)
X
Resets (Above)
Intel
UDDR5
0x00000000
Reset Hex Value:
UDDR5
Description
UDDR6
0x00000000
Reset Hex Value:
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(UDDR5)
8 7
(8-Bit Data)
0 0 0 0 0 0 0
(UDDR6)
8 7
(8-Bit Data)
0 0 0 0 0 0 0
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