Time Synchronization Hardware Assist (TSYNC)—Intel
Line of Network Processors
19.5.2.6
RawSystemTime_Low Register
Register Name:
Block
RegBlockAddress
Base Address:
RawSystemTime_Low Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
This system time register is a read-only register of the raw system time. It is,
therefore, not loadable and reflects the local time in the module.
• The lower 32 bits of the 64-bit system time are read in this register.
• The upper 32 bits are read in the RawSystemTime_High register.
RawSystemTi
31:0
When a user reads system time with this pair of registers, no latching of
me_Low
system time occurs, which means that the system time could increment
between the reading of the lower 32 bits in this register and the upper 32 bits
in the RawSystemTime_High register. The user must account for this and deal
with possible increments between reads of the two registers in firmware.
RawSystemTime_High Register
19.5.2.7
Register Name:
Block
RegBlockAddress
Base Address:
RawSystemTime_High Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
This register contains the upper 32 bits of system time. When you want to
read or write the system time, this register typically first accesses the
RawSystemTi
RawSystemTime_Low Register. This register pair contains the raw system
31:0
me_High
timer value, and no latching of system time occurs when the lower half is
read. Time could increment between the reading of the lower 32 bits in the
RawSystemTime_Low register and the reading of this register.
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
TS_RSysTimeLo
Offset Address
RawSystemTime_Low[31:0]
TS_RSysTimeLo
Description
TS_RSysTimeHI
Offset Address
RawSystemTime_High[31:0]
TS_RSysTimeHi
Description
®
Intel
IXP45X and Intel
®
IXP46X Product
0x018
Reset Value
Access:
8
7
6
5
Reset
Value
0x01C
Reset Value
Access:
8
7
6
5
Reset
Value
®
IXP46X Product Line of Network Processors
0x0
(See below.)
4
3
2
1
0
Access
0
RO
0x0
(See below.)
4
3
2
1
0
Access
0
RO
Developer's Manual
843
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