Ddri Sdram Write Cycle - Intel IXP45X Developer's Manual

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Memory Controller—Intel
11.2.2.11

DDRI SDRAM Write Cycle

All write transactions to the DDRI SDRAM are posted to the MCU in the memory
transaction queues. This implies that the transaction completes between a given port
and corresponding unit prior to data being written to the SDRAM array. Once the MARB
issues a write command from a memory transaction queue to the MCU DDRI Control
Block, the paging logic makes a hit/miss comparison (illustrated in
performance is best for page hits and therefore the MCUs behavior is different for the
hit and miss scenario.
Write transactions require ECC codes to be generated and stored in the SDRAM array
with the data being written. The behavior is different depending on the size of the data
being written.
in more detail.
For a page hit, the MCU does not need to open the page (assert DDRI_RAS_N) and
avoids the RAS-to-CAS delay achieving greater performance. The waveform for a write
including the row activation in the case of a page miss is illustrated in
page hit, the two cycles required for row activation are saved resulting in lower first
word write latency.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
"Error Correction and Detection" on page 614
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Figure 104). The
explains the ECC algorithm
Figure 115. For a
Developer's Manual
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