Register Descriptions Ethernet Macs - Intel IXP45X Developer's Manual

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Ethernet MACs—Intel IXP45X and Intel
The Core Control (CORE_CONTROL) Register was added to allow the Intel XScale
processor to have some control over the Ethernet coprocessor. Configuring bit 4 of the
Core Control (CORE_CONTROL) Register can configure as an input or as an output the
MDC clock.
Setting bit 4 of the Core Control (CORE_CONTROL) Register to logic 1 enables the
IXP45X/IXP46X network processors to drive the MDC clock. Setting bit 4 of the Core
Control (CORE_CONTROL) Register to logic 0 enables an external source to drive the
MDC clock. The IXP45X/IXP46X network processors become a recipient of that MDC
clock.
Configuring bit 3 of the Core Control (CORE_CONTROL) Register can configure the
Transmit Engine to send a JAM sequence if a new packet starts to be received. Setting
bit 3 of the Core Control (CORE_CONTROL) Register to logic 1 enables the IXP45X/
IXP46X network processors to send a JAM sequence if a new packet is receive.
Setting bit 3 of the Core Control (CORE_CONTROL) Register to logic 0 allows the
Transmit Engine to function in normal mode of operation. Configuring bit 2 of the Core
Control (CORE_CONTROL) Register causes the Transmit FIFO to be flushed. Any
packets that are currently in the Transmit FIFO are discarded.
Setting bit 2 of the Core Control (CORE_CONTROL) Register to logic 1 clears the xMII
Interface Transmit FIFO. Setting bit 2 of the Core Control (CORE_CONTROL) Register
back to logic 0 allows the Transmit FIFO to resume normal mode of operation.
Configuring bit 1 of the Core Control (CORE_CONTROL) Register causes the Receive
FIFO to be flushed. Any packets that are currently in the Receive FIFO are discarded.
Setting bit 1 of the Core Control (CORE_CONTROL) Register to logic 1 clears the xMII
Interface Receive FIFO. Setting bit 1 of the Core Control (CORE_CONTROL) Register
back to logic 0 allows the Receive FIFO to resume normal mode of operation. Bit 0 of
the Core Control (CORE_CONTROL) Register controls the reset state of the Media
Access Controller (MAC) contained within the Ethernet coprocessor.
Setting bit 0 of the Core Control (CORE_CONTROL) Register back to logic 1 causes the
Media Access Controller to be reset. De-assertion (setting bit 0 to logic 0) allows the
Media Access Controller to resume operation in a fully reset state.
This register needs to be manipulated using Intel-supplied APIs. Failure to manipulate
this register with Intel-supplied APIs will result in unpredictable behavior.
The Random-Seed Register is an 8-bit register used to support PHYs that support Auto
MDI/MDI-X detection. The Random-Seed Register value is the value that is used to feed
the Linear-Feedback Shift Register that is used to select which configuration to start
initialization.
The Random-Seed Register needs to be manipulated using Intel-supplied APIs. Failure
to manipulate this could result in unpredictable behavior.
6.2

Register Descriptions Ethernet MACs

The internal registers shown below are accessible via the APB bus interface.
Unspecified addresses are reserved and should not be written; if read, a zero value will
be returned.
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Intel IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer's Manual
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