Uart Timing Diagram - Intel IXP45X Developer's Manual

Intel
Figure 183. UART Timing Diagram
Start
Bit Definition
UART
TXD or RXD
The serial port can operate in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte
transmit FIFO holds data coming from the Intel XScale processor to be transmitted on
the serial link, and the 64-byte Receive FIFO, buffers data received from the serial link
until the data is read by the Intel XScale processor. In Non-FIFO mode, data will be
transmitted and received using two registers - the Transmit-Holding Register and the
Receive-Buffer Register - along with the UART control, status and interrupt registers.
The UARTs include a programmable baud rate generator capable of dividing the
14.7456-MHz, UART input clock by divisors of 1 to (2
drive the internal transmitter and receiver logic. The 14.7456-MHz, UART input clock is
generated internally to the IXP45X/IXP46X network processors.
Interrupts can be programmed to the user's requirements, minimizing the computing
required to handle the communications link. Each UART can be operated in a polled or
an interrupt driven environment as selected by software.
The maximum baud rate supported by the UART is 921.6 Kbps. The divisors
programmed in divisor latch registers should be equal to or greater than 1 for proper
operation. The device UARTs may be initialized by setting 13 configuration registers.
14.2 Feature List
• Microprocessor Interface Control via Advanced Peripheral Bus (APB)
• Adds or deletes standard asynchronous communications bits (start, stop, and
parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud rate generator allows division of clock by 1 to (2
generates an internal 16X clock
• Modem control functions (cts_n and rts_n)
• Fully programmable serial-interface characteristics:
• 5, 6, 7, or 8-bit characters
• Even, odd, or no parity detection
• 1, 1-1/2, or 2 stop bit generation
• Baud rate generation (up to 921kbps)
• False start bit detection
• 64-byte Transmit FIFO
• 64-byte Receive FIFO
• Complete status reporting capability
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
750
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IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous
Data Data Data Data
<0> <1> <2> <3>
LSB
Data Data Data Data
<4> <5> <6> <7>
MSB
16
1) and produces a 16X clock to
–
Receiver-Transmitter (UART)
Parity Stop Stop
Bit Bit 1 Bit 2
B4321-01
16
–1) and
August 2006
Order Number: 306262-004US