Udc Active; Udc Resume (Rsm); Resume Interrupt Request (Resir); Suspend Interrupt Request (Susir) - Intel IXP45X Developer's Manual

8.5.1.2

UDC Active

The read-only UDC Active (UDA) bit can be read to determine if the UDC is currently
active or in a USB reset. This bit is only valid when the UDC is enabled. A 0 indicates
that the UDC is currently receiving a USB reset from the USB Host. A 1 indicates that
the UDC is currently involved in a transaction.
8.5.1.3

UDC Resume (RSM)

When the UDC is in a suspend state, this bit can be written to force the UDC into a non-
idle state (K state) for 3 ms to perform a remote wake-up operation. If the host PC
does not start a wake-up sequence in 3 ms, the UDC returns to the suspend mode.
This bit is a trigger bit for the UDC and is automatically cleared.
8.5.1.4

Resume Interrupt Request (RESIR)

The resume interrupt request bit is set if the SRM bit in the UDC control register is
cleared, the UDC is currently in the suspended state, and the USB is driven with
resume signalling.
8.5.1.5

Suspend Interrupt Request (SUSIR)

The suspend interrupt request register is set when the USB remains idle for more than
6 ms. The SUSIR bit retains state so software can determine that the USB is idle. If
SRM is 0, SUSIR being set will not generate an interrupt but status continues to be
updated.
8.5.1.6

Suspend/Resume Interrupt Mask (SRM)

The suspend/resume interrupt mask (SRM) masks or enables the suspend interrupt
request to the interrupt controller. When SRM is 1, the interrupt is masked and the
setting of SUSIR will not generate an interrupt. When SRM is 0, the setting of SUSIR
generates an interrupt when the USB is idle for more than 6 ms.
Programming SRM does not affect the state of SUSIR.
8.5.1.7

Reset Interrupt Request (RSTIR)

The reset interrupt request register is set when the host issues a reset. When the host
issues a reset, the entire UDC is reset. The RSTIR bit retains its state so software can
determine that the design was reset. If REM is 0, RSTIR being set does not generate an
interrupt but status continues to be updated.
8.5.1.8

Reset Interrupt Mask (REM)

The reset interrupt mask (REM) masks or enables the reset interrupt request to the
interrupt controller. When REM is 1, the interrupt is masked and the setting of RSTIR
does not generate an interrupt. When REM is 0, the RSTIR setting generates an
interrupt when the USB host controller issues an UDC reset.
Programming REM does not affect the state of RSTIR.
The UDE bit is cleared to 0, which disables the UDC following a Intel XScale processor
reset. Writes to reserved bits are ignored and reads return zeros.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
292
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device
Controller
August 2006
Order Number: 306262-004US