Empty Asynchronous Schedule Detection; Restarting Asynchronous Schedule Before Eof; Asynchronous Schedule List With Annotation To Mark Head Of List - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
Software may re-use the memory associated with the removed queue heads after it
observes the Interrupt on Async Advance status bit is set to a one, following assertion
of the doorbell. Software should acknowledge the Interrupt on Async Advance status as
indicated in the USBSTS register, before using the doorbell handshake again.
9.14.8.3

Empty Asynchronous Schedule Detection

The Enhanced Host Controller Interface uses two bits to detect when the asynchronous
schedule is empty. The queue head data structure (see
Structure Layout" on page
software to mark a queue head as being the head of the reclaim list. The Enhanced
Host Controller Interface also keeps a 1-bit flag in the USBSTS register (Reclamation)
that is set to a zero when the Enhanced Interface Host Controller observes a queue
head with the H-bit set to a one. The reclamation flag in the status register is set to one
when any USB transaction from the asynchronous schedule is executed (or whenever
the asynchronous schedule starts, see
on page
If the Enhanced Host Controller Interface ever encounters an H-bit of one and a
Reclamation bit of zero, the EHCI controller simply stops traversal of the asynchronous
schedule.
An example illustrating the H-bit in a schedule is illustrated in
Figure 62.

Asynchronous Schedule List with Annotation to Mark Head of List

Reclamation Flag
USBCMD
USBSTS
ASYNCHLISTADDR
Operational
Registers
Software must ensure there is at most one queue head with the H-bit set to a one, and
that it is always coherent with respect to the schedule.
9.14.8.4

Restarting Asynchronous Schedule Before EOF

There are many situations where the host controller will detect an empty list long
before the end of the micro-frame. It is important to remember that under many
circumstances the schedule traversal has stopped due to Nak/Nyet responses from all
endpoints.
An example of particular interest is when a start-split for a bulk endpoint occurs early in
the micro-frame. Given the EHCI simple traversal rules, the complete-split for that
transaction may Nak/Nyet out very quickly. If it is the only item in the schedule, then
the host controller will cease traversal of the Asynchronous schedule very early in the
micro-frame. In order to provide reasonable service to this endpoint, the host controller
should issue the complete-split before the end of the current micro-frame, instead of
waiting until the next micro-frame. When the reason for host controller idling
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
404) defines an H-bit in the queue head, which allows
438).
1: Transaction Executed
0: Head of List Screen
Typ T
Horizontal Ptr 01
1
Operational Area
H
List Head
"Asynchronous Schedule Traversal: Start Event"
Typ T
0 01
Horizontal Ptr
0
Operational Area
H
Asynchronous Schedule
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Figure 50, "Queue Head
Figure 62.
Typ T
0 01
Horizontal Ptr
0
Operational Area
H
Developer's Manual
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