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Time Synchronization Hardware Assist (TSYNC)—Intel
Line of Network Processors
19.5.2.17
TS_Channel_Event Register (Per Channel)
Register Name:
Block
RegBlockAddress
Base Address:
Time Synchronization Channel Event Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
31:2
Reserved
Reserved for future use.
Receive Snapshot Locked. This bit is automatically set when a Delay_Req
message in Master mode, or a Sync message in Slave mode, is received and
the ta bit in the corresponding TS_Channel_Control register is clear. It
1
rxs
indicates that the current system time value has been captured in the
RECV_Snapshot register and that further changes to the RECV_Snapshot are
now locked out. To clear this bit, write a '1' to it.
Transmit Snapshot Locked. This bit is automatically set when a Sync
message in Master mode, or a Delay_Req message in Slave mode, is
transmitted and the ta bit in the corresponding TS_Channel_Control register is
0
txs
clear. It indicates that the current system time value has been captured in the
XMIT_Snapshot register and that further changes to the XMIT_Snapshot are
now locked out. To clear this bit, write a '1' to it.
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
TS_Ch_Event
Offset Address
Reserved
*Address offsets per channel...
Channel 0 = 0x044
Channel 1 = 0x064
Channel 2 = 0x084
TS_Ch_Event
Description
®
Intel
IXP45X and Intel
®
IXP46X Product
0x044*
Reset Value
Access:
8
7
6
5
®
IXP46X Product Line of Network Processors
x00
(See below.)
4
3
2
1
0
Reset
Access
Value
x
x
0
RW
0
RW
Developer's Manual
849
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