Message Byte Formats - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Table 51
Table 51.

Message Byte Formats

Message Name
Check-Pointed Direct Branch
Indirect Branch
Check-Pointed Indirect Branch
Notes:
1. Direct branches include Intel
2. Indirect branches include Intel
THUMB bx, blx(1) and blx(2); and THUMB pop.
3.6.13.1.1 Exception Message Byte
When any kind of exception occurs, an exception message is placed in the trace buffer.
In an exception message byte, the message type bit (M) is always 0.
The vector exception (VVV) field is used to specify bits[4:2] of the vector address
(offset from the base of default or relocated vector table). The vector allows the host
SW to identify which exception occurred.
The incremental word count (CCCC) is the instruction count since the last control flow
change (not including the current instruction for undef, SWI, and pre-fetch abort). The
instruction count includes instructions that were executed and conditional instructions
that were not executed due to the condition of the instruction not matching the CC
flags.
A count value of 0 indicates that 0 instructions executed since the last control flow
change and the current exception. For example, if a branch is immediate followed by a
SWI, a direct branch exception message (for the branch) is followed by an exception
message (for the SWI) in the trace buffer. The count value in the exception message
will be 0, meaning that 0 instructions executed after the last control flow change (the
branch) and before the current control flow change (the SWI). Instead of the SWI, if an
IRQ was handled immediately after the branch (before any other instructions
executed), the count would still be 0, since no instructions executed after the branch
and before the interrupt was handled.
A count of 0b1111 indicates that 15 instructions executed between the last branch and
the exception. In this case, an exception was either caused by the 16th instruction (if it
is an undefined instruction exception, pre-fetch abort, or SWI) or handled before the
16th instruction executed (for FIQ, IRQ, or data abort).
3.6.13.1.2 Non-Exception Message Byte
Non-exception message bytes are used for direct branches, indirect branches, and
rollovers.
In a non-exception message byte, the four-bit message type field (MMMM) specifies the
type of message (refer to
The incremental word count (CCCC) is the instruction count since the last control flow
change (excluding the current branch). The instruction count includes instructions that
were executed and conditional instructions that were not executed due to the condition
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
shows all of the possible trace messages.
Message Byte Type
Exception
1
Direct Branch
1
2
2
Roll-over
®
Table
Message Byte Format
exception
non-exception
non-exception
non-exception
non-exception
non-exception
*
StrongARM and THUMB bl, b.
® *
StrongARM ldm, ldr, and dproc to PC; Intel
51).
® ®
Intel IXP45X and Intel
# Address
0b0VVV CCCC
0b1000 CCCC
0b1100 CCCC
0b1001 CCCC
0b1101 CCCC
0b1111 1111
®
StrongARM
IXP46X Product Line of Network Processors
Developer's Manual
Bytes
0
0
0
4
4
0
*
and
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