Receive Short Packet (Rsp); Udc Endpoint 13 Control/Status Register - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
8.5.14.8

Receive Short Packet (RSP)

The UDC uses the receive short packet bit to indicate that the received OUT packet in
the active buffer currently being read is a short packet or zero-sized packet. This bit is
updated by the UDC after the last byte is read from the active buffer and reflects the
status of the new active buffer.
If UDCCS12[RSP] is a 1 and UDCCS12[RNE] is a 0, it indicates a zero-length packet. If
a zero-length packet is present, the Intel XScale processor must not read the data
register. UDCCS12[RSP] is cleared when the next OUT packet is received.
Register Name:
0 x C800 B040
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 12 Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.15

UDC Endpoint 13 Control/Status Register

The UDC Endpoint 13 Control Status Register contains four bits that are used to
operate Endpoint 13, an Isochronous IN endpoint.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Receive short packet (read only).
RSP
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
RNE 0 = Receive FIFO empty.
1 = Receive FIFO not empty.
Force stall (read/write).
FST
1 = Issue STALL handshakes to OUT tokens.
Sent stall (read/write 1 to clear).
SST
1 = STALL handshake was sent.
(Reserved)
(Reserved). Always reads zero.
Receive packet complete (read/write 1 to clear).
RPC 0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS 0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
Intel
UDCCS12
0 x 00000000
Reset Hex Value:
UDCCS12
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0
(UDCCS13)
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