Debug Modes; Halt Mode; Monitor Mode; Debug Control And Status Register (Dcsr) - Intel IXP45X Developer's Manual

Intel
Software access to all debug registers must be done in privileged mode. User mode
access will generate an undefined instruction exception. Specifying registers which do
not exist has unpredictable results.
The TX and RX registers, certain bits in the TXRXCTRL register, and certain bits in the
DCSR can be accessed by a debugger through the JTAG interface.
3.6.3

Debug Modes

The debug unit for the IXP45X/IXP46X network processors, when used with a debugger
application, allows software running on the IXP45X/IXP46X network processors' target
to be debugged. The debug unit allows the debugger to stop program execution and re-
direct execution to a debug handling routine. Once program execution has stopped, the
debugger can examine or modify processor state, coprocessor state, or memory. The
debugger can then restart execution of the application.
On the IXP45X/IXP46X network processors, one of two debug modes can be entered:

• Halt mode

• Monitor mode

3.6.3.1 Halt Mode
When the debug unit is configured for halt mode, the reset vector is overloaded to
serve as the debug vector. A new processor mode, DEBUG mode (CPSR[4:0] = 0x15),
is added to allow debug exceptions to be handled similarly to other types of Intel
StrongARM
When a debug exception occurs, the processor switches to debug mode and redirects
execution to a debug handler, via the reset vector. After the debug handler begins
execution, the debugger can communicate with the debug handler to examine or alter
processor state or memory through the JTAG interface.
The debug handler can be downloaded and locked directly into the instruction cache
through JTAG so external memory is not required to contain debug handler code.
3.6.3.2 Monitor Mode
In monitor mode, debug exceptions are handled like Intel
®
or Intel
When a debug exception occurs, the processor switches to abort mode and branches to
a debug handler using the pre-fetch abort vector or data abort vector. The debugger
then communicates with the debug handler to access processor state or memory
contents.
3.6.4

Debug Control and Status Register (DCSR)

The DCSR register is the main control register for the debug unit.
format of the register. The DCSR register can be accessed in privileged modes by
software running on the core or by a debugger through the JTAG interface. Refer to
"SELDCSR JTAG Register" on page 125
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
112
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
*
exceptions.
*
StrongARM data aborts, depending on the cause of the exception.
®
StrongARM
for details about accessing DCSR through JTAG.
®
Processor
®
*
prefetch aborts
Table 35 shows the
August 2006
Order Number: 306262-004US