Intel Strongarm Architecture Implementation Options; Big-Endian Versus Little-Endian; 26-Bit Architecture; Thumb - Intel IXP45X Developer's Manual

Intel
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3.8.2 Intel
3.8.2.1

Big-Endian versus Little-Endian

The IXP45X/IXP46X network processors can operate in big or little endian mode. The B-
bit of the Control Register, coprocessor 15, register 1, bit 7 (see
contained within the IXP45X/IXP46X network processors selects the endianess mode of
the Intel XScale processor.
Note: This bit takes effect even if the MMU is disabled.
If you choose little endian then you have further options that control whether address
and/or data coherency modes. Refer P-Attribute bit in the MMU (see
"Page (P) Attribute Bit" on page
BYTE_SWAP_ENABLE
Definition" on page
Note: The NPEs on the IXP45X/IXP46X network processors are Big-Endian only; so if you
change the endianess of the Intel XScale processor to little endian for your operating
system, then this has an impact on how the NPEs and Intel XScale processor exchange
data. The Intel
3.8.2.2

26-Bit Architecture

The Intel XScale processor does not support 26-bit architecture.
3.8.2.3

Thumb

The Intel XScale processor supports the thumb instruction set.
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3.8.2.4 Intel
The Intel XScale processor implements Intel StrongARM's DSP-enhanced instruction set
which is a set of instructions that boost the performance of signal processing
applications. There are new multiply instructions that operate on 16-bit data values and
new saturation instructions. Saturated instructions are used to ensure accuracy during
DSP operations to ensure the signed extension is maintained during an overflow
arithmetic operation. Further information on saturated integer arithmetic can be found
in the ARM* Architecture Reference Manual.
Some of the new instructions are:
• SMLAxy — 32<=16x16+32
• SMLAWy — 32<=32x16+32
• SMLALxy — 64<=16x16+64
• SMULxy — 32<=16x16
• SMULWy — 32<=32x16
• QADD — Adds two registers and saturates the result if an overflow occurred
• QDADD — Doubles and saturates one of the input registers then add and saturate
• QSUB — Subtracts two registers and saturates the result if an overflow occurred
• QDSUB — Doubles and saturates one of the input registers then subtract and
saturate
The Intel XScale processor also implements Load Two words (LDRD), Store Two Words
(STRD) and cache preload (PLD) instructions with the following implementation notes:
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
168
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
*
StrongARM Architecture Implementation Options
(Table 231, "Expansion Bus Configuration Register 1-Bit
710).
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IXP400 Software Release handles this.
*
StrongARM DSP-Enhanced Instruction Set
70) and Expansion Bus Configuration Register 1, Bit 8,
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Processor
Section 3.5.1.2)
Section 3.1.1.1,
August 2006
Order Number: 306262-004US