Data Cache Organization - Intel IXP45X Developer's Manual

Intel
The data cache is virtually addressed and virtually tagged. The data cache supports
write-back and write-through caching policies. The data cache always allocates a line in
the cache when a cacheable read miss occurs and will allocate a line into the cache on
a cacheable write miss when write allocate is specified by its page attribute. Page
attribute bits determine whether a line gets allocated into the data cache or mini-data
cache.
Figure 10.

Data Cache Organization

Example: 32-Kbyte cache
Set Index
This example shows
Set 0 being selected
by the set index.
Word Select
Byte Select
Data Address (Virtual) — 32-Kbyte Cache
31
The mini-data cache is 2 Kbytes in size. The 2-Kbyte mini data cache has 32 sets and is
two-way set associative. Each way of a set contains 32 bytes (one cache line) and one
valid bit. There also exist two dirty bits for every line, one for the lower 16 bytes and
the other one for the upper 16 bytes. When a store hits the cache the dirty bit
associated with it is set. The replacement policy is a round-robin algorithm.
Figure 11, "Mini-Data Cache Organization" on page 87
and how the data address is used to access the cache.
The mini-data cache is virtually addressed and virtually tagged and supports the same
caching policies as the data cache. However, lines can't be locked into the mini-data
cache.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Set 1
way 0
Set 0
way 1
way 0
way 1
CAM
CAM
way 31
way 31
Tag
(4 bytes to Destination Register)
Tag
Set 31
way 0
way 1
CAM
32 bytes (cache line)
32 bytes (cache line)
way 31
DATA
DATA
Byte Alignment
Sign Extension
Data Word
10
shows the cache organization
®
Processor
32 bytes (cache line)
DATA
CAM: Content Addressable Memory
9 5 4 2 1 0
Set Index Word
August 2006
Order Number: 306262-004US
Byte
B4332-01